{"id":"https://openalex.org/W1554061286","doi":"https://doi.org/10.1109/vlsi-dat.2015.7114567","title":"Full-custom all-digital phase locked loop for clock generation","display_name":"Full-custom all-digital phase locked loop for clock generation","publication_year":2015,"publication_date":"2015-04-01","ids":{"openalex":"https://openalex.org/W1554061286","doi":"https://doi.org/10.1109/vlsi-dat.2015.7114567","mag":"1554061286"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2015.7114567","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2015.7114567","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design, Automation and Test(VLSI-DAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025086348","display_name":"Mu-lee Huang","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Mu-lee Huang","raw_affiliation_strings":["Department of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan","[Department of Electrical Engineering, National Chiao-Tung University, Hsinchu, Taiwan]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"[Department of Electrical Engineering, National Chiao-Tung University, Hsinchu, Taiwan]","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010248769","display_name":"Chung-Chih Hung","orcid":"https://orcid.org/0000-0002-5817-712X"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chung-Chih Hung","raw_affiliation_strings":["Department of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan","[Department of Electrical Engineering, National Chiao-Tung University, Hsinchu, Taiwan]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"[Department of Electrical Engineering, National Chiao-Tung University, Hsinchu, Taiwan]","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5025086348"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.1973,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.55925725,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8830373883247375},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8501431941986084},{"id":"https://openalex.org/keywords/time-to-digital-converter","display_name":"Time-to-digital converter","score":0.730174720287323},{"id":"https://openalex.org/keywords/digitally-controlled-oscillator","display_name":"Digitally controlled oscillator","score":0.644279956817627},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5381072759628296},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5140100717544556},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.5119794607162476},{"id":"https://openalex.org/keywords/ring-oscillator","display_name":"Ring oscillator","score":0.48878929018974304},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.4358363449573517},{"id":"https://openalex.org/keywords/phase-detector","display_name":"Phase detector","score":0.42567822337150574},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.4255833327770233},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.24171236157417297},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23501935601234436},{"id":"https://openalex.org/keywords/delay-line-oscillator","display_name":"Delay line oscillator","score":0.2259262204170227},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21687409281730652},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.14336401224136353},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.1274278163909912},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.11047753691673279},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10954195261001587}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8830373883247375},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8501431941986084},{"id":"https://openalex.org/C99594498","wikidata":"https://www.wikidata.org/wiki/Q2434524","display_name":"Time-to-digital converter","level":4,"score":0.730174720287323},{"id":"https://openalex.org/C167872736","wikidata":"https://www.wikidata.org/wiki/Q5276224","display_name":"Digitally controlled oscillator","level":5,"score":0.644279956817627},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5381072759628296},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5140100717544556},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.5119794607162476},{"id":"https://openalex.org/C104111718","wikidata":"https://www.wikidata.org/wiki/Q2153973","display_name":"Ring oscillator","level":3,"score":0.48878929018974304},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.4358363449573517},{"id":"https://openalex.org/C110086884","wikidata":"https://www.wikidata.org/wiki/Q2085341","display_name":"Phase detector","level":3,"score":0.42567822337150574},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.4255833327770233},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.24171236157417297},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23501935601234436},{"id":"https://openalex.org/C26907483","wikidata":"https://www.wikidata.org/wiki/Q5253479","display_name":"Delay line oscillator","level":4,"score":0.2259262204170227},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21687409281730652},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.14336401224136353},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.1274278163909912},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.11047753691673279},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10954195261001587},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat.2015.7114567","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2015.7114567","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design, Automation and Test(VLSI-DAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.800000011920929}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2062952706","https://openalex.org/W2067333289","https://openalex.org/W2119220251","https://openalex.org/W2137120286","https://openalex.org/W2152338756","https://openalex.org/W2153743315","https://openalex.org/W2163268258","https://openalex.org/W2166268103","https://openalex.org/W6684281454"],"related_works":["https://openalex.org/W2401428732","https://openalex.org/W2992346850","https://openalex.org/W2415980476","https://openalex.org/W1988254802","https://openalex.org/W2044826848","https://openalex.org/W145049781","https://openalex.org/W3005757405","https://openalex.org/W2583032843","https://openalex.org/W2786180788","https://openalex.org/W2040664936"],"abstract_inverted_index":{"A":[0,16],"novel":[1],"approach":[2],"of":[3,71,81],"constructing":[4],"an":[5,47],"All-Digital":[6],"Phase":[7],"Locked":[8],"Loop":[9],"(ADPLL)":[10],"is":[11,22,36,59,74,84,91,101,115],"presented":[12,37],"in":[13,107],"this":[14,45],"paper.":[15],"3-Step":[17],"symmetric":[18],"Time-to-Digital":[19],"Converter":[20],"(TDC)":[21],"proposed":[23],"with":[24,64],"both":[25],"long":[26],"dynamic":[27,69],"range":[28,70],"and":[29,77,98,104],"high":[30],"resolution.":[31],"The":[32,56,68,95],"Upper-and-Lower-boundaries-Cut-off-Determination":[33],"(ULCD)":[34],"logic":[35],"for":[38],"a":[39],"full-custom":[40],"digital":[41],"loop":[42],"filter.":[43],"With":[44],"method,":[46],"all-digital":[48],"PLL":[49],"can":[50],"be":[51],"designed":[52,60],"without":[53],"synthesis":[54],"procedures.":[55],"Digitally-Controlled":[57],"Oscillator":[58],"by":[61],"ring":[62],"architecture":[63],"periodic":[65],"variation":[66],"linear.":[67],"the":[72,78,82,108,112],"TDC":[73,83],"7.7":[75],"ns":[76],"finest":[79],"resolution":[80],"only":[85,92,116],"12.7":[86],"ps.":[87],"System":[88],"locked":[89],"time":[90],"1.62":[93],"us.":[94],"rms":[96],"jitter":[97,100],"P-P":[99],"4.68":[102],"ps":[103,106],"38.68":[105],"measurement":[109],"results.":[110],"And":[111],"power":[113],"dissipation":[114],"7.55":[117],"mW.":[118]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}