{"id":"https://openalex.org/W1546046289","doi":"https://doi.org/10.1109/vlsi-dat.2015.7114551","title":"Evaluation methods of computer memory system","display_name":"Evaluation methods of computer memory system","publication_year":2015,"publication_date":"2015-04-01","ids":{"openalex":"https://openalex.org/W1546046289","doi":"https://doi.org/10.1109/vlsi-dat.2015.7114551","mag":"1546046289"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2015.7114551","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2015.7114551","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design, Automation and Test(VLSI-DAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113824454","display_name":"Shih\u2010Lien Lu","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Shih-Lien Lu","raw_affiliation_strings":["Intel Corporation, Hillsboro Oregon, USA","Intel Corporation, Hillsboro, Oregon 97124, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro Oregon, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Hillsboro, Oregon 97124, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5113824454"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.02613319,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8317204713821411},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5601666569709778},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5456311702728271},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.516326367855072},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.5150315761566162},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.5086499452590942},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.4946546256542206},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.47651994228363037},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.47456032037734985},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.4452659487724304},{"id":"https://openalex.org/keywords/non-uniform-memory-access","display_name":"Non-uniform memory access","score":0.4329605996608734},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.4271033704280853},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.4196888506412506},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.41586318612098694},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.40647679567337036},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4036102592945099},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32171571254730225},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3069746494293213},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.23066461086273193}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8317204713821411},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5601666569709778},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5456311702728271},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.516326367855072},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.5150315761566162},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.5086499452590942},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.4946546256542206},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.47651994228363037},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.47456032037734985},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.4452659487724304},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.4329605996608734},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.4271033704280853},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.4196888506412506},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.41586318612098694},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.40647679567337036},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4036102592945099},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32171571254730225},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3069746494293213},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.23066461086273193}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat.2015.7114551","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2015.7114551","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design, Automation and Test(VLSI-DAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.4099999964237213}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1595118008","https://openalex.org/W2010369165","https://openalex.org/W2038101378","https://openalex.org/W2039742886","https://openalex.org/W2058521308","https://openalex.org/W2095232189","https://openalex.org/W2113247440","https://openalex.org/W2153306514","https://openalex.org/W2155764480","https://openalex.org/W2162639668","https://openalex.org/W3137094666","https://openalex.org/W4251534053","https://openalex.org/W6815746053"],"related_works":["https://openalex.org/W254684032","https://openalex.org/W2247651031","https://openalex.org/W2606565524","https://openalex.org/W2096506606","https://openalex.org/W2041174925","https://openalex.org/W4321458411","https://openalex.org/W99066252","https://openalex.org/W2117533242","https://openalex.org/W4233816696","https://openalex.org/W2145484885"],"abstract_inverted_index":{"Memory":[0,49],"is":[1,11,113],"a":[2,90,108,126],"necessary":[3],"part":[4],"of":[5,22,32,40,77,85,87,104,130,140],"any":[6],"computing":[7,33,57,109],"system":[8,58,63,110,132],"as":[9,16,18,70,80,82],"it":[10,112],"used":[12,50,106],"to":[13,35,55,61,115],"store":[14],"data":[15,44],"well":[17,81],"programs.":[19],"The":[20],"amount":[21,76,103],"main":[23],"memory":[24,105,131],"(DRAM)":[25],"has":[26,65],"been":[27,66,94],"increasing":[28,67,95],"for":[29,46],"all":[30],"segments":[31],"devices":[34],"accommodate":[36],"an":[37],"ever-increasing":[38],"number":[39,84],"applications":[41],"installed":[42],"and":[43,134,138],"needed":[45],"those":[47],"applications.":[48],"at":[51],"the":[52,74,83,97,102,136],"microarchitectural":[53],"level":[54],"enhance":[56],"performance":[59],"or":[60],"reduce":[62],"power":[64],"in":[68,96,107,119],"capacity":[69,79],"well.":[71],"For":[72],"example,":[73],"total":[75],"cache":[78,88],"levels":[86],"on":[89],"microprocessor":[91],"chip":[92],"have":[93],"last":[98],"couple":[99],"decades.":[100],"As":[101],"increases,":[111],"important":[114],"evaluate":[116],"design":[117,133],"trade-offs":[118],"details.":[120],"In":[121],"this":[122],"paper":[123],"we":[124],"compare":[125],"few":[127],"evaluation":[128],"approaches":[129],"discuss":[135],"pros":[137],"cons":[139],"these":[141],"approaches.":[142]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}