{"id":"https://openalex.org/W2079163302","doi":"https://doi.org/10.1109/vlsi-dat.2012.6212666","title":"A hardware in the loop design methodology for FPGA system and its application to complex functions","display_name":"A hardware in the loop design methodology for FPGA system and its application to complex functions","publication_year":2012,"publication_date":"2012-04-01","ids":{"openalex":"https://openalex.org/W2079163302","doi":"https://doi.org/10.1109/vlsi-dat.2012.6212666","mag":"2079163302"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2012.6212666","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2012.6212666","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of Technical Program of 2012 VLSI Design, Automation and Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://oa.upm.es/20903/","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110003060","display_name":"Guixuan Liang","orcid":null},"institutions":[{"id":"https://openalex.org/I88060688","display_name":"Universidad Polit\u00e9cnica de Madrid","ror":"https://ror.org/03n6nwv02","country_code":"ES","type":"education","lineage":["https://openalex.org/I88060688"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Guixuan Liang","raw_affiliation_strings":["Centro de Electr\u00f3nica Industrial, Universidad Polit\u00e9cnica de Madrid, Madrid, Spain","[Centro de Electr\u00f3nica Industrial, Universidad Polit\u00e9cnica de Madrid, Spain]"],"affiliations":[{"raw_affiliation_string":"Centro de Electr\u00f3nica Industrial, Universidad Polit\u00e9cnica de Madrid, Madrid, Spain","institution_ids":["https://openalex.org/I88060688"]},{"raw_affiliation_string":"[Centro de Electr\u00f3nica Industrial, Universidad Polit\u00e9cnica de Madrid, Spain]","institution_ids":["https://openalex.org/I88060688"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012981301","display_name":"Danping He","orcid":"https://orcid.org/0000-0002-0917-5013"},"institutions":[{"id":"https://openalex.org/I88060688","display_name":"Universidad Polit\u00e9cnica de Madrid","ror":"https://ror.org/03n6nwv02","country_code":"ES","type":"education","lineage":["https://openalex.org/I88060688"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Danping He","raw_affiliation_strings":["Centro de Electr\u00f3nica Industrial, Universidad Polit\u00e9cnica de Madrid, Madrid, Spain","[Centro de Electr\u00f3nica Industrial, Universidad Polit\u00e9cnica de Madrid, Spain]"],"affiliations":[{"raw_affiliation_string":"Centro de Electr\u00f3nica Industrial, Universidad Polit\u00e9cnica de Madrid, Madrid, Spain","institution_ids":["https://openalex.org/I88060688"]},{"raw_affiliation_string":"[Centro de Electr\u00f3nica Industrial, Universidad Polit\u00e9cnica de Madrid, Spain]","institution_ids":["https://openalex.org/I88060688"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022228753","display_name":"Jorge Portilla","orcid":"https://orcid.org/0000-0003-4896-6229"},"institutions":[{"id":"https://openalex.org/I88060688","display_name":"Universidad Polit\u00e9cnica de Madrid","ror":"https://ror.org/03n6nwv02","country_code":"ES","type":"education","lineage":["https://openalex.org/I88060688"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"J. Portilla","raw_affiliation_strings":["Centro de Electr\u00f3nica Industrial, Universidad Polit\u00e9cnica de Madrid, Madrid, Spain","[Centro de Electr\u00f3nica Industrial, Universidad Polit\u00e9cnica de Madrid, Spain]"],"affiliations":[{"raw_affiliation_string":"Centro de Electr\u00f3nica Industrial, Universidad Polit\u00e9cnica de Madrid, Madrid, Spain","institution_ids":["https://openalex.org/I88060688"]},{"raw_affiliation_string":"[Centro de Electr\u00f3nica Industrial, Universidad Polit\u00e9cnica de Madrid, Spain]","institution_ids":["https://openalex.org/I88060688"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018896607","display_name":"Teresa Riesgo","orcid":"https://orcid.org/0000-0003-0532-8681"},"institutions":[{"id":"https://openalex.org/I88060688","display_name":"Universidad Polit\u00e9cnica de Madrid","ror":"https://ror.org/03n6nwv02","country_code":"ES","type":"education","lineage":["https://openalex.org/I88060688"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"T. Riesgo","raw_affiliation_strings":["Centro de Electr\u00f3nica Industrial, Universidad Polit\u00e9cnica de Madrid, Madrid, Spain","[Centro de Electr\u00f3nica Industrial, Universidad Polit\u00e9cnica de Madrid, Spain]"],"affiliations":[{"raw_affiliation_string":"Centro de Electr\u00f3nica Industrial, Universidad Polit\u00e9cnica de Madrid, Madrid, Spain","institution_ids":["https://openalex.org/I88060688"]},{"raw_affiliation_string":"[Centro de Electr\u00f3nica Industrial, Universidad Polit\u00e9cnica de Madrid, Spain]","institution_ids":["https://openalex.org/I88060688"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5110003060"],"corresponding_institution_ids":["https://openalex.org/I88060688"],"apc_list":null,"apc_paid":null,"fwci":0.7429,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.74556138,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8867794275283813},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7216749787330627},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5345482230186462},{"id":"https://openalex.org/keywords/fast-fourier-transform","display_name":"Fast Fourier transform","score":0.5196908116340637},{"id":"https://openalex.org/keywords/orthogonal-frequency-division-multiplexing","display_name":"Orthogonal frequency-division multiplexing","score":0.5182511806488037},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.48663339018821716},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.4748421311378479},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.43575239181518555},{"id":"https://openalex.org/keywords/systems-design","display_name":"Systems design","score":0.4341641962528229},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.4276786744594574},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.41125449538230896},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14997822046279907},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.06942364573478699},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06836065649986267}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8867794275283813},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7216749787330627},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5345482230186462},{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.5196908116340637},{"id":"https://openalex.org/C40409654","wikidata":"https://www.wikidata.org/wiki/Q375889","display_name":"Orthogonal frequency-division multiplexing","level":3,"score":0.5182511806488037},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48663339018821716},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.4748421311378479},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.43575239181518555},{"id":"https://openalex.org/C31352089","wikidata":"https://www.wikidata.org/wiki/Q3750474","display_name":"Systems design","level":2,"score":0.4341641962528229},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.4276786744594574},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.41125449538230896},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14997822046279907},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.06942364573478699},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06836065649986267},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/vlsi-dat.2012.6212666","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2012.6212666","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of Technical Program of 2012 VLSI Design, Automation and Test","raw_type":"proceedings-article"},{"id":"pmh:oai:oa.upm.es:20903","is_oa":true,"landing_page_url":"http://oa.upm.es/20903/","pdf_url":null,"source":{"id":"https://openalex.org/S4306402421","display_name":"Archivo Digital UPM (Universidad Polit\u00e9cnica de Madrid)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I88060688","host_organization_name":"Universidad Polit\u00e9cnica de Madrid","host_organization_lineage":["https://openalex.org/I88060688"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on | Proceedings of VLSI, Design, Automation and Test (VLSI-DAT) | 23/04/2012 - 25/04/2012 | Hsinchu (Taiwan)","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:oa.upm.es:20903","is_oa":true,"landing_page_url":"http://oa.upm.es/20903/","pdf_url":null,"source":{"id":"https://openalex.org/S4306402421","display_name":"Archivo Digital UPM (Universidad Polit\u00e9cnica de Madrid)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I88060688","host_organization_name":"Universidad Polit\u00e9cnica de Madrid","host_organization_lineage":["https://openalex.org/I88060688"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on | Proceedings of VLSI, Design, Automation and Test (VLSI-DAT) | 23/04/2012 - 25/04/2012 | Hsinchu (Taiwan)","raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[{"score":0.5,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1488505464","https://openalex.org/W1972485640","https://openalex.org/W1989778348","https://openalex.org/W1989893660","https://openalex.org/W2015458074","https://openalex.org/W2096965884","https://openalex.org/W2115228192","https://openalex.org/W2119353116","https://openalex.org/W2148951605","https://openalex.org/W3148402870"],"related_works":["https://openalex.org/W2013702403","https://openalex.org/W2582722586","https://openalex.org/W4298128640","https://openalex.org/W2131435457","https://openalex.org/W1868968390","https://openalex.org/W2947632305","https://openalex.org/W2372374202","https://openalex.org/W2783374954","https://openalex.org/W202914971","https://openalex.org/W2136141785"],"abstract_inverted_index":{"In":[0],"this":[1],"work,":[2],"a":[3,26],"unified":[4],"algorithm-architecture-circuit":[5],"co-design":[6],"environment":[7],"for":[8,24,55,89],"complex":[9,94],"FPGA":[10,29,95],"system":[11,30,65,96],"development":[12,47],"is":[13,18,68,82],"presented.":[14],"The":[15],"main":[16],"objective":[17],"to":[19,43,73,86],"find":[20],"an":[21,71],"efficient":[22,79],"methodology":[23,81],"designing":[25],"configurable":[27],"optimized":[28],"by":[31],"using":[32],"as":[33,36,42,70],"few":[34],"efforts":[35],"possible":[37],"in":[38],"verification":[39],"stage,":[40],"so":[41],"speed":[44],"up":[45],"the":[46,75],"period.":[48],"A":[49],"proposed":[50,76],"high":[51],"performance":[52],"FFT/iFFT":[53],"processor":[54],"Multiband":[56],"Orthogonal":[57],"Frequency":[58],"Division":[59],"Multiplexing":[60],"Ultra":[61],"Wideband":[62],"(MB-OFDM":[63],"UWB)":[64],"design":[66,80],"process":[67],"given":[69],"example":[72],"demonstrate":[74],"methodology.":[77],"This":[78],"tested":[83],"and":[84,98],"considered":[85],"be":[87],"suitable":[88],"almost":[90],"all":[91],"types":[92],"of":[93],"designs":[97],"verifications.":[99]},"counts_by_year":[{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}