{"id":"https://openalex.org/W1993559586","doi":"https://doi.org/10.1109/vlsi-dat.2012.6212635","title":"A high-speed dual-phase processing pipelined domino circuit design with a built-in performance adjusting mechanism","display_name":"A high-speed dual-phase processing pipelined domino circuit design with a built-in performance adjusting mechanism","publication_year":2012,"publication_date":"2012-04-01","ids":{"openalex":"https://openalex.org/W1993559586","doi":"https://doi.org/10.1109/vlsi-dat.2012.6212635","mag":"1993559586"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2012.6212635","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2012.6212635","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of Technical Program of 2012 VLSI Design, Automation and Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041509052","display_name":"Ching-Hwa Cheng","orcid":"https://orcid.org/0000-0003-0587-237X"},"institutions":[{"id":"https://openalex.org/I4880106","display_name":"Feng Chia University","ror":"https://ror.org/05vhczg54","country_code":"TW","type":"education","lineage":["https://openalex.org/I4880106"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Ching-Hwa Cheng","raw_affiliation_strings":["Department of Electronic Engineering, Feng Chia University, TaiChun, Taiwan","Dept. of Electronic Engineering, Feng Chia University, 100, Wenhwa Road, Seatwen, Taichung Taiwan R.O.C.#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Feng Chia University, TaiChun, Taiwan","institution_ids":["https://openalex.org/I4880106"]},{"raw_affiliation_string":"Dept. of Electronic Engineering, Feng Chia University, 100, Wenhwa Road, Seatwen, Taichung Taiwan R.O.C.#TAB#","institution_ids":["https://openalex.org/I4880106"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5022312926","display_name":"Jiun-In Guo","orcid":"https://orcid.org/0000-0003-0402-2621"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jiun-In Guo","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, HsinChu, Taiwan","Department of Electronics Engineering, National Chiao Tung University, 1001 Ta Hsueh Road, Hsinchu, Taiwan (R.O.C)"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, HsinChu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, 1001 Ta Hsueh Road, Hsinchu, Taiwan (R.O.C)","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5041509052"],"corresponding_institution_ids":["https://openalex.org/I4880106"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.06657792,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/domino-logic","display_name":"Domino logic","score":0.6021657586097717},{"id":"https://openalex.org/keywords/domino","display_name":"Domino","score":0.5986231565475464},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5958561301231384},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5800970196723938},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.57647305727005},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5189192295074463},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5083140730857849},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4983022212982178},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.46288296580314636},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37110304832458496},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3223528563976288},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.30446502566337585},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2836666703224182},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23763710260391235},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.10276836156845093}],"concepts":[{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.6021657586097717},{"id":"https://openalex.org/C2776416436","wikidata":"https://www.wikidata.org/wiki/Q3751781","display_name":"Domino","level":3,"score":0.5986231565475464},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5958561301231384},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5800970196723938},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.57647305727005},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5189192295074463},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5083140730857849},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4983022212982178},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.46288296580314636},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37110304832458496},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3223528563976288},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.30446502566337585},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2836666703224182},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23763710260391235},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.10276836156845093},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C161790260","wikidata":"https://www.wikidata.org/wiki/Q82264","display_name":"Catalysis","level":2,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat.2012.6212635","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2012.6212635","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of Technical Program of 2012 VLSI Design, Automation and Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.6600000262260437,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2108971405","https://openalex.org/W2114025510"],"related_works":["https://openalex.org/W4231158717","https://openalex.org/W2059009651","https://openalex.org/W3174071739","https://openalex.org/W2150513440","https://openalex.org/W4254482168","https://openalex.org/W18274992","https://openalex.org/W2098328611","https://openalex.org/W2100009051","https://openalex.org/W2118796996","https://openalex.org/W2306283289"],"abstract_inverted_index":{"A":[0,84],"high-speed":[1,34],"dual-phase":[2,32],"domino":[3,87],"circuit":[4],"design":[5,22,72,105],"with":[6,36,75,90],"high":[7,24],"performance":[8,25,39,57,110,121],"and":[9,94],"reliable":[10],"characteristics":[11],"is":[12,113],"proposed.":[13],"The":[14,27,51],"cell-based":[15,70],"automatic":[16],"synthesis":[17],"flow":[18],"supports":[19,120],"the":[20,61,78,103,116],"quick":[21],"of":[23,30,77],"chips.":[26],"test":[28,52],"chip":[29,53,124],"a":[31,37,55,69,108],"64-bit":[33],"multiplier":[35],"built-in":[38,109],"adjustment":[40,111,122],"mechanism":[41,112,119],"has":[42,81],"been":[43,82],"successfully":[44],"validated":[45],"using":[46],"TSMC":[47],"0.18um":[48],"CMOS":[49,64],"technology.":[50],"shows":[54],"2.7X":[56],"improvement":[58],"compared":[59],"to":[60,101],"conventional":[62],"static":[63],"logic":[65],"design.":[66,117],"In":[67],"addition,":[68],"synthesizable":[71],"CAD":[73],"flow,":[74],"consideration":[76],"skew-tolerant":[79],"issue":[80],"established.":[83],"latched":[85],"type":[86],"cell":[88],"library":[89],"noise-alleviation,":[91],"charge":[92],"sharing,":[93],"crosstalk":[95],"alleviation":[96],"abilities":[97],"was":[98],"also":[99],"developed":[100],"support":[102],"proposed":[104],"flow.":[106],"Finally,":[107],"conducted":[114],"within":[115],"This":[118],"after":[123],"fabrication,":[125],"under":[126],"clock":[127],"skew":[128],"considerations.":[129]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
