{"id":"https://openalex.org/W4403277978","doi":"https://doi.org/10.1109/vdat63601.2024.10705696","title":"Design, Validation and Characterization of Number Theoretic Transform IP Core","display_name":"Design, Validation and Characterization of Number Theoretic Transform IP Core","publication_year":2024,"publication_date":"2024-09-01","ids":{"openalex":"https://openalex.org/W4403277978","doi":"https://doi.org/10.1109/vdat63601.2024.10705696"},"language":"en","primary_location":{"id":"doi:10.1109/vdat63601.2024.10705696","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vdat63601.2024.10705696","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 28th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113801170","display_name":"Koraboyina Anusha","orcid":null},"institutions":[{"id":"https://openalex.org/I114845381","display_name":"National Institute of Technology Calicut","ror":"https://ror.org/03yyd7552","country_code":"IN","type":"education","lineage":["https://openalex.org/I114845381"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Koraboyina Anusha","raw_affiliation_strings":["National Institute of Electronics and Information Technology,Calicut,Kerala"],"affiliations":[{"raw_affiliation_string":"National Institute of Electronics and Information Technology,Calicut,Kerala","institution_ids":["https://openalex.org/I114845381"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041637200","display_name":"Rajalakshmi Nandakumar","orcid":"https://orcid.org/0000-0002-1601-148X"},"institutions":[{"id":"https://openalex.org/I114845381","display_name":"National Institute of Technology Calicut","ror":"https://ror.org/03yyd7552","country_code":"IN","type":"education","lineage":["https://openalex.org/I114845381"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"R NandaKumar","raw_affiliation_strings":["National Institute of Electronics and Information Technology,Calicut,Kerala"],"affiliations":[{"raw_affiliation_string":"National Institute of Electronics and Information Technology,Calicut,Kerala","institution_ids":["https://openalex.org/I114845381"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5113801170"],"corresponding_institution_ids":["https://openalex.org/I114845381"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.18192264,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9839000105857849,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9839000105857849,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9455000162124634,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9316999912261963,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/characterization","display_name":"Characterization (materials science)","score":0.5761358737945557},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.5579339861869812},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5494316816329956},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.08861058950424194},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.081490159034729}],"concepts":[{"id":"https://openalex.org/C2780841128","wikidata":"https://www.wikidata.org/wiki/Q5073781","display_name":"Characterization (materials science)","level":2,"score":0.5761358737945557},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.5579339861869812},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5494316816329956},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.08861058950424194},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.081490159034729},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vdat63601.2024.10705696","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vdat63601.2024.10705696","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 28th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2467320551","https://openalex.org/W2786640091","https://openalex.org/W3065439923","https://openalex.org/W3160317696","https://openalex.org/W3185075495","https://openalex.org/W3216309469","https://openalex.org/W4207043551","https://openalex.org/W4383899661","https://openalex.org/W6847067301"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2748952813","https://openalex.org/W3107994849","https://openalex.org/W4247143848","https://openalex.org/W2009883749","https://openalex.org/W2735573198","https://openalex.org/W2390279801","https://openalex.org/W29442446","https://openalex.org/W2358668433","https://openalex.org/W4396701345"],"abstract_inverted_index":{"The":[0,49,80,188,249,263],"Number":[1,216],"Theoretic":[2,217],"Transform":[3,60,218],"(NTT)":[4],"is":[5,16,37,124,231,280,296],"a":[6,19,54,69,77,85,94,125,150],"mathematical":[7],"concept":[8],"that":[9,46,62,181,242,298],"solves":[10],"complex":[11],"problems":[12],"in":[13,40,84,93,108,120,138,149,303],"cryptography.":[14],"It":[15,36,66,295],"recognized":[17],"as":[18,113],"very":[20],"efficient":[21],"transform":[22,81],"for":[23,91,127,132,178,255,310,317],"the":[24,57,74,100,133,136,145,172,176,195,215,224,227,244,256,259,278,283,288,304,307,321,325],"multiplication":[25],"of":[26,43,56,71,76,135,209,214,226,258,272,291],"two":[27,270],"polynomials":[28],"with":[29,68,73,202,206,269,277],"high":[30],"degrees,":[31],"which":[32],"have":[33,252],"integer":[34],"coefficients.":[35],"widely":[38],"used":[39],"practical":[41],"implementations":[42],"cryptography":[44],"schemes":[45],"are":[47,142,300],"lattice-based.":[48],"NTT":[50,101,137,260,289],"can":[51],"be":[52,148,234],"considered":[53],"variant":[55],"Discrete":[58],"Fourier":[59],"(DFT)":[61],"operates":[63],"on":[64,144,171,194,282,320],"integers.":[65],"deals":[67],"ring":[70],"integers":[72],"modulus":[75,146,305],"prime":[78],"number.":[79],"involves":[82],"arithmetic":[83,118],"modular":[86],"approach,":[87],"making":[88],"it":[89,230],"suitable":[90],"computations":[92,290],"finite":[95,121],"field.":[96],"However,":[97],"solutions":[98],"implementing":[99],"suffer":[102],"from":[103],"computational":[104,318],"inefficiencies,":[105],"limiting":[106],"applications":[107],"various":[109],"critical":[110],"domains":[111],"such":[112],"cryptography,":[114],"signal":[115],"processing,":[116],"and":[117,163,246],"operations":[119],"fields.":[122],"There":[123,141],"need":[126,177],"an":[128,165,236],"optimized":[129],"hardware":[130,180],"solution":[131],"computation":[134],"VLSI":[139,186],"design.":[140,312],"limitations":[143,302],"to":[147,160,175,222,233,286],"particular":[151],"form.":[152],"To":[153],"address":[154],"this":[155,157,311,314],"gap,":[156],"work":[158,189,264],"aims":[159],"design,":[161],"validate,":[162],"characterize":[164],"Intellectual":[166],"Property":[167],"(IP)":[168],"Core":[169],"based":[170],"NTT,":[173],"catering":[174],"specialized":[179],"facilitates":[182],"integration":[183],"into":[184],"diverse":[185],"designs.":[187],"has":[190,219,239,265],"been":[191,220,240,253,266],"carried":[192,267],"out":[193,268],"ARTY":[196],"Artix-7":[197],"100T":[198],"FPGA":[199,279],"Development":[200],"board":[201],"part":[203],"number":[204],"XC7A100TCSG324-1":[205],"multiple":[207],"inputs":[208,323],"different":[210,273],"dimensions.":[211,274],"RTL":[212],"implementation":[213],"done":[221,281],"verify":[223],"accuracy":[225,319],"computation.":[228],"Once":[229],"found":[232],"accurate,":[235],"IP":[237,261],"core":[238],"developed":[241],"meets":[243],"timing":[245],"power":[247],"constraints.":[248],"performance":[250],"metrics":[251],"calculated":[254],"characterization":[257],"core.":[262],"models":[271,285],"On-chip":[275],"debugging":[276],"created":[284],"validate":[287],"given":[292,322],"input":[293],"sequences.":[294],"observed":[297],"there":[299],"no":[301],"or":[306],"twiddle":[308],"factor":[309],"Additionally,":[313],"design":[315],"accounts":[316],"within":[324],"specified":[326],"data":[327],"limits.":[328]},"counts_by_year":[],"updated_date":"2025-12-27T23:08:20.325037","created_date":"2025-10-10T00:00:00"}