{"id":"https://openalex.org/W2185184524","doi":"https://doi.org/10.1109/test.2015.7342411","title":"Optimizing delay tests at the memory boundary","display_name":"Optimizing delay tests at the memory boundary","publication_year":2015,"publication_date":"2015-10-01","ids":{"openalex":"https://openalex.org/W2185184524","doi":"https://doi.org/10.1109/test.2015.7342411","mag":"2185184524"},"language":"en","primary_location":{"id":"doi:10.1109/test.2015.7342411","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2015.7342411","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Test Conference (ITC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5018025856","display_name":"Kelly Ockunzzi","orcid":"https://orcid.org/0000-0002-3541-8306"},"institutions":[{"id":"https://openalex.org/I4210142027","display_name":"GlobalFoundries (Germany)","ror":"https://ror.org/045jad561","country_code":"DE","type":"company","lineage":["https://openalex.org/I35662394","https://openalex.org/I4210142027"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Kelly A. Ockunzzi","raw_affiliation_strings":["GLOBALFOUNDRIES Inc"],"affiliations":[{"raw_affiliation_string":"GLOBALFOUNDRIES Inc","institution_ids":["https://openalex.org/I4210142027"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020892804","display_name":"M.R. Ouellette","orcid":null},"institutions":[{"id":"https://openalex.org/I4210142027","display_name":"GlobalFoundries (Germany)","ror":"https://ror.org/045jad561","country_code":"DE","type":"company","lineage":["https://openalex.org/I35662394","https://openalex.org/I4210142027"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Michael R. Ouellette","raw_affiliation_strings":["GLOBALFOUNDRIES Inc"],"affiliations":[{"raw_affiliation_string":"GLOBALFOUNDRIES Inc","institution_ids":["https://openalex.org/I4210142027"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030006566","display_name":"K. Gorman","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kevin W. Gorman","raw_affiliation_strings":["INVECAS, Vermont, USA"],"affiliations":[{"raw_affiliation_string":"INVECAS, Vermont, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5018025856"],"corresponding_institution_ids":["https://openalex.org/I4210142027"],"apc_list":null,"apc_paid":null,"fwci":0.646,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.70325313,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7105098366737366},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.5612220764160156},{"id":"https://openalex.org/keywords/boundary-scan","display_name":"Boundary scan","score":0.5482731461524963},{"id":"https://openalex.org/keywords/test-suite","display_name":"Test suite","score":0.5343097448348999},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5212119817733765},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.4429948627948761},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.44215989112854004},{"id":"https://openalex.org/keywords/boundary","display_name":"Boundary (topology)","score":0.4307402968406677},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.41836944222450256},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4124164581298828},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.375349760055542},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3677167296409607},{"id":"https://openalex.org/keywords/test-case","display_name":"Test case","score":0.19687306880950928},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16151279211044312},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.14107835292816162},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.12938961386680603},{"id":"https://openalex.org/keywords/machine-learning","display_name":"Machine learning","score":0.10352179408073425},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08908528089523315}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7105098366737366},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.5612220764160156},{"id":"https://openalex.org/C992767","wikidata":"https://www.wikidata.org/wiki/Q895156","display_name":"Boundary scan","level":3,"score":0.5482731461524963},{"id":"https://openalex.org/C151552104","wikidata":"https://www.wikidata.org/wiki/Q7705809","display_name":"Test suite","level":4,"score":0.5343097448348999},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5212119817733765},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.4429948627948761},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.44215989112854004},{"id":"https://openalex.org/C62354387","wikidata":"https://www.wikidata.org/wiki/Q875399","display_name":"Boundary (topology)","level":2,"score":0.4307402968406677},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.41836944222450256},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4124164581298828},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.375349760055542},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3677167296409607},{"id":"https://openalex.org/C128942645","wikidata":"https://www.wikidata.org/wiki/Q1568346","display_name":"Test case","level":3,"score":0.19687306880950928},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16151279211044312},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.14107835292816162},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.12938961386680603},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.10352179408073425},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08908528089523315},{"id":"https://openalex.org/C152877465","wikidata":"https://www.wikidata.org/wiki/Q208042","display_name":"Regression analysis","level":2,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2015.7342411","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2015.7342411","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Test Conference (ITC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.6000000238418579}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1489923824","https://openalex.org/W1588305013","https://openalex.org/W2029243854","https://openalex.org/W2095626533","https://openalex.org/W2143535677","https://openalex.org/W2144511081","https://openalex.org/W2169342007","https://openalex.org/W6674147355"],"related_works":["https://openalex.org/W2098533503","https://openalex.org/W2048563045","https://openalex.org/W1852363244","https://openalex.org/W2172250424","https://openalex.org/W2107525390","https://openalex.org/W2166065438","https://openalex.org/W2764440971","https://openalex.org/W4230966676","https://openalex.org/W1503491858","https://openalex.org/W2111803469"],"abstract_inverted_index":{"Delay":[0],"faults":[1,40,106],"on":[2,107],"the":[3,51,58,64,68,80,108,114,120],"inputs":[4],"and":[5,41,57,66,92,123],"outputs":[6],"of":[7,50,53,82,116,144,148],"memories":[8,65,84],"embedded":[9],"in":[10,19,95,128],"an":[11],"integrated":[12,154],"circuit":[13,155],"are":[14],"difficult":[15],"to":[16,37,63,67,71],"cover":[17],"efficiently":[18],"manufacturing":[20,44,98],"test.":[21],"A":[22],"complicated":[23],"approach,":[24],"separate":[25],"from":[26,131],"standard":[27,97],"digital":[28],"logic":[29,70],"tests":[30,103],"or":[31],"memory":[32,109,126],"built-in":[33],"self-test,":[34],"is":[35,85,93],"needed":[36],"target":[38],"these":[39,73],"further":[42],"improve":[43],"quality.":[45],"This":[46],"paper":[47],"discusses":[48],"some":[49],"challenges":[52],"implementing":[54],"this":[55],"approach":[56],"design-for-test":[59],"changes":[60],"we":[61],"made":[62],"surrounding":[69],"address":[72],"challenges.":[74],"Our":[75,87],"optimized":[76],"method":[77,139],"for":[78,104,152],"testing":[79,124],"boundaries":[81],"repaired":[83],"presented.":[86],"implementation":[88],"has":[89],"been":[90],"validated":[91],"included":[94],"our":[96,138],"test":[99,121,150],"suite.":[100],"It":[101],"improves":[102],"delay":[105],"functional":[110],"boundary":[111],"by":[112],"minimizing":[113],"capture":[115],"unknown":[117],"data,":[118],"simplifying":[119],"sequences,":[122],"different":[125],"types":[127],"parallel.":[129],"Results":[130],"five":[132],"32nm":[133],"industry":[134],"parts":[135],"show":[136],"that":[137],"enables":[140],"entirely":[141],"automatic":[142],"generation":[143],"a":[145],"compact":[146],"set":[147],"high-coverage":[149],"patterns":[151],"any":[153],"design.":[156]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}