{"id":"https://openalex.org/W2162464888","doi":"https://doi.org/10.1109/test.2007.4437603","title":"Testing for systematic defects based on DFM guidelines","display_name":"Testing for systematic defects based on DFM guidelines","publication_year":2007,"publication_date":"2007-01-01","ids":{"openalex":"https://openalex.org/W2162464888","doi":"https://doi.org/10.1109/test.2007.4437603","mag":"2162464888"},"language":"en","primary_location":{"id":"doi:10.1109/test.2007.4437603","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2007.4437603","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE International Test Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050345689","display_name":"Dongok Kim","orcid":"https://orcid.org/0000-0002-4097-2889"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Dongok Kim","raw_affiliation_strings":["Purdue University, West Lafayette, IN, USA"],"affiliations":[{"raw_affiliation_string":"Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038248556","display_name":"M. Enamul Amyeen","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Enamul Amyeen","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100896813","display_name":"Srikanth Venkataraman","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Srikanth Venkataraman","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032651920","display_name":"Irith Pomeranz","orcid":"https://orcid.org/0000-0002-5491-7282"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Irith Pomeranz","raw_affiliation_strings":["Purdue University, West Lafayette, IN, USA"],"affiliations":[{"raw_affiliation_string":"Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5097205179","display_name":"Swagato Basumallick","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Swagato Basumallick","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110267533","display_name":"Berni Landau","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Berni Landau","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5050345689"],"corresponding_institution_ids":["https://openalex.org/I219193219"],"apc_list":null,"apc_paid":null,"fwci":2.5997,"has_fulltext":false,"cited_by_count":33,"citation_normalized_percentile":{"value":0.90054232,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-for-manufacturability","display_name":"Design for manufacturability","score":0.9254473447799683},{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.6851385831832886},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.588904619216919},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.5886811017990112},{"id":"https://openalex.org/keywords/pentium","display_name":"Pentium","score":0.5270015597343445},{"id":"https://openalex.org/keywords/quality","display_name":"Quality (philosophy)","score":0.43534982204437256},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25406917929649353},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.24118521809577942},{"id":"https://openalex.org/keywords/mechanical-engineering","display_name":"Mechanical engineering","score":0.11347690224647522}],"concepts":[{"id":"https://openalex.org/C62064638","wikidata":"https://www.wikidata.org/wiki/Q553878","display_name":"Design for manufacturability","level":2,"score":0.9254473447799683},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.6851385831832886},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.588904619216919},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.5886811017990112},{"id":"https://openalex.org/C46268123","wikidata":"https://www.wikidata.org/wiki/Q214314","display_name":"Pentium","level":2,"score":0.5270015597343445},{"id":"https://openalex.org/C2779530757","wikidata":"https://www.wikidata.org/wiki/Q1207505","display_name":"Quality (philosophy)","level":2,"score":0.43534982204437256},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25406917929649353},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.24118521809577942},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.11347690224647522},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2007.4437603","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2007.4437603","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE International Test Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.47999998927116394,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":37,"referenced_works":["https://openalex.org/W63318650","https://openalex.org/W270615609","https://openalex.org/W1494166260","https://openalex.org/W1526749485","https://openalex.org/W1531696936","https://openalex.org/W1555407400","https://openalex.org/W1564266201","https://openalex.org/W1586707510","https://openalex.org/W1600468096","https://openalex.org/W1637395447","https://openalex.org/W1644767855","https://openalex.org/W2051907727","https://openalex.org/W2098171066","https://openalex.org/W2098374349","https://openalex.org/W2102556246","https://openalex.org/W2104400227","https://openalex.org/W2109768518","https://openalex.org/W2112978605","https://openalex.org/W2118744758","https://openalex.org/W2119205109","https://openalex.org/W2129021480","https://openalex.org/W2129212061","https://openalex.org/W2133505378","https://openalex.org/W2139730802","https://openalex.org/W2141193558","https://openalex.org/W2154418718","https://openalex.org/W2155059120","https://openalex.org/W2156747864","https://openalex.org/W2161824088","https://openalex.org/W2164152101","https://openalex.org/W2167622257","https://openalex.org/W2171020103","https://openalex.org/W2171908682","https://openalex.org/W4235228648","https://openalex.org/W4239330251","https://openalex.org/W6602516640","https://openalex.org/W6675373693"],"related_works":["https://openalex.org/W1597195064","https://openalex.org/W3154683910","https://openalex.org/W1846734616","https://openalex.org/W1545378222","https://openalex.org/W2915007006","https://openalex.org/W2094969048","https://openalex.org/W994558755","https://openalex.org/W2129938370","https://openalex.org/W3134543635","https://openalex.org/W3035935536"],"abstract_inverted_index":{"With":[0],"shrinking":[1],"feature":[2],"sizes":[3],"of":[4,9,77],"manufacturing":[5],"processes,":[6],"the":[7,52,75],"occurrence":[8],"systematic":[10,25,45,82],"defects":[11],"is":[12,92],"expected":[13],"to":[14,37,60],"increase.":[15],"In":[16],"this":[17],"paper,":[18],"we":[19],"present":[20],"techniques":[21],"for":[22,44,74,94],"identifying":[23,85],"potential":[24,42,86],"defect":[26,56],"candidates":[27],"from":[28],"design-for-manufacturing":[29],"(DFM)":[30],"layout":[31,39],"guidelines.":[32],"DFM":[33],"guidelines":[34],"are":[35,49,58,67],"tightened":[36],"find":[38],"locations":[40],"as":[41],"sites":[43],"defects,":[46],"affected":[47],"transistors":[48],"identified":[50],"at":[51],"schematic":[53],"level,":[54],"and":[55,84],"behaviors":[57],"translated":[59],"gate":[61],"level":[62],"logic":[63],"faults.":[64],"Experimental":[65],"results":[66],"presented":[68],"on":[69],"an":[70],"Intel":[71],"Pentium\u00ea4":[72],"design":[73],"evaluation":[76],"existing":[78],"tests":[79],"in":[80],"screening":[81],"failures":[83],"test":[87,90,96],"holes.":[88],"Additional":[89],"content":[91],"generated":[93],"improving":[95],"quality.":[97]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-03-17T09:09:15.849793","created_date":"2025-10-10T00:00:00"}