{"id":"https://openalex.org/W3022691227","doi":"https://doi.org/10.1109/socc46988.2019.1570548362","title":"A 2.7-Gb/s Clock and Data Recovery Circuit Based on D/PLL","display_name":"A 2.7-Gb/s Clock and Data Recovery Circuit Based on D/PLL","publication_year":2019,"publication_date":"2019-09-01","ids":{"openalex":"https://openalex.org/W3022691227","doi":"https://doi.org/10.1109/socc46988.2019.1570548362","mag":"3022691227"},"language":"en","primary_location":{"id":"doi:10.1109/socc46988.2019.1570548362","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc46988.2019.1570548362","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103235928","display_name":"Yousheng Lin","orcid":"https://orcid.org/0000-0002-9982-3167"},"institutions":[{"id":"https://openalex.org/I162838928","display_name":"National Chung Hsing University","ror":"https://ror.org/05vn3ca78","country_code":"TW","type":"education","lineage":["https://openalex.org/I162838928"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"You-Sheng Lin","raw_affiliation_strings":["Department of Electrical Engineering, National Chung Hsing University, 145 Xingda Rd., South Dist., Taichung City 402, Taiwan (R.O.C.)"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Chung Hsing University, 145 Xingda Rd., South Dist., Taichung City 402, Taiwan (R.O.C.)","institution_ids":["https://openalex.org/I162838928"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031864203","display_name":"Miao-Shan Li","orcid":null},"institutions":[{"id":"https://openalex.org/I162838928","display_name":"National Chung Hsing University","ror":"https://ror.org/05vn3ca78","country_code":"TW","type":"education","lineage":["https://openalex.org/I162838928"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Miao-Shan Li","raw_affiliation_strings":["Department of Electrical Engineering, National Chung Hsing University, 145 Xingda Rd., South Dist., Taichung City 402, Taiwan (R.O.C.)"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Chung Hsing University, 145 Xingda Rd., South Dist., Taichung City 402, Taiwan (R.O.C.)","institution_ids":["https://openalex.org/I162838928"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066897196","display_name":"Ching\u2010Yuan Yang","orcid":"https://orcid.org/0000-0002-5335-3665"},"institutions":[{"id":"https://openalex.org/I162838928","display_name":"National Chung Hsing University","ror":"https://ror.org/05vn3ca78","country_code":"TW","type":"education","lineage":["https://openalex.org/I162838928"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ching-Yuan Yang","raw_affiliation_strings":["Department of Electrical Engineering, National Chung Hsing University, 145 Xingda Rd., South Dist., Taichung City 402, Taiwan (R.O.C.)"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Chung Hsing University, 145 Xingda Rd., South Dist., Taichung City 402, Taiwan (R.O.C.)","institution_ids":["https://openalex.org/I162838928"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5103235928"],"corresponding_institution_ids":["https://openalex.org/I162838928"],"apc_list":null,"apc_paid":null,"fwci":0.1192,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.5079862,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":"32","issue":null,"first_page":"284","last_page":"288"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9894999861717224,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.9454176425933838},{"id":"https://openalex.org/keywords/retiming","display_name":"Retiming","score":0.8021755218505859},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.7468967437744141},{"id":"https://openalex.org/keywords/clock-recovery","display_name":"Clock recovery","score":0.6209583282470703},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.6013123989105225},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6000256538391113},{"id":"https://openalex.org/keywords/data-recovery","display_name":"Data recovery","score":0.5763275027275085},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.550325334072113},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.5189792513847351},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.5189487934112549},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.513974130153656},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4968152344226837},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.4498818516731262},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.42120233178138733},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3856383264064789},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3140696585178375},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.29838234186172485},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20997294783592224}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.9454176425933838},{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.8021755218505859},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.7468967437744141},{"id":"https://openalex.org/C2779835379","wikidata":"https://www.wikidata.org/wiki/Q2348121","display_name":"Clock recovery","level":4,"score":0.6209583282470703},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.6013123989105225},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6000256538391113},{"id":"https://openalex.org/C529754248","wikidata":"https://www.wikidata.org/wiki/Q1054772","display_name":"Data recovery","level":2,"score":0.5763275027275085},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.550325334072113},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.5189792513847351},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.5189487934112549},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.513974130153656},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4968152344226837},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.4498818516731262},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.42120233178138733},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3856383264064789},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3140696585178375},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.29838234186172485},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20997294783592224}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socc46988.2019.1570548362","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socc46988.2019.1570548362","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.800000011920929}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2113608937","https://openalex.org/W2115434507","https://openalex.org/W2126057508","https://openalex.org/W2131216244","https://openalex.org/W2788379598","https://openalex.org/W6679325135"],"related_works":["https://openalex.org/W2139338465","https://openalex.org/W3150034945","https://openalex.org/W99106843","https://openalex.org/W2104362597","https://openalex.org/W127191621","https://openalex.org/W2323221746","https://openalex.org/W2615366277","https://openalex.org/W2338811059","https://openalex.org/W1564896735","https://openalex.org/W2129957622"],"abstract_inverted_index":{"In":[0],"the":[1,41,48,56,68],"paper,":[2],"a":[3,23,30],"3Gb/s":[4],"clock":[5,31,65],"and":[6,29,43,67],"data":[7,70,77],"recovery":[8,32],"(CDR)":[9],"is":[10],"presented":[11],"for":[12,26,34],"high-speed":[13],"embedded-clock":[14],"interconnects":[15],"in":[16,52],"LCD":[17],"drivers.":[18],"The":[19,37],"CDR":[20,39],"consists":[21],"of":[22],"decision":[24],"circuit":[25,33],"realizing":[27,35],"regeneration,":[28],"retiming.":[36],"proposed":[38],"combines":[40],"delay-locked":[42],"phase-locked":[44],"loops":[45],"to":[46],"improve":[47],"jitter":[49,62,74],"peaking.":[50],"Implemented":[51],"0.18-\u03bcm":[53],"CMOS":[54],"technology,":[55],"recovered":[57,69],"clocks":[58],"have":[59,71],"5.27ps":[60],"peak-to-peak":[61,73],"at":[63,75],"100MHz":[64],"frequency,":[66],"5.34ps":[72],"2.7-Gb/s":[76],"rate.":[78],"This":[79],"work":[80],"consumes":[81],"72.52mW":[82],"with":[83],"1.8V":[84],"power":[85],"supply.":[86]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
