{"id":"https://openalex.org/W4413096013","doi":"https://doi.org/10.1109/smacd65553.2025.11092178","title":"Hybrid AI-Optimization Method for Latent Defect Detection Through Test Transistor Insertion in Analog Circuits","display_name":"Hybrid AI-Optimization Method for Latent Defect Detection Through Test Transistor Insertion in Analog Circuits","publication_year":2025,"publication_date":"2025-07-07","ids":{"openalex":"https://openalex.org/W4413096013","doi":"https://doi.org/10.1109/smacd65553.2025.11092178"},"language":"en","primary_location":{"id":"doi:10.1109/smacd65553.2025.11092178","is_oa":false,"landing_page_url":"https://doi.org/10.1109/smacd65553.2025.11092178","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Sankhya Bhattacharya","orcid":null},"institutions":[{"id":"https://openalex.org/I99464096","display_name":"KU Leuven","ror":"https://ror.org/05f950310","country_code":"BE","type":"education","lineage":["https://openalex.org/I99464096"]}],"countries":["BE"],"is_corresponding":true,"raw_author_name":"Sankhya Bhattacharya","raw_affiliation_strings":["KU Leuven,Dept. Electrical Engineering (ESAT- MICAS),Leuven,Belgium"],"affiliations":[{"raw_affiliation_string":"KU Leuven,Dept. Electrical Engineering (ESAT- MICAS),Leuven,Belgium","institution_ids":["https://openalex.org/I99464096"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5029270525","display_name":"Georges Gielen","orcid":"https://orcid.org/0000-0002-4061-9428"},"institutions":[{"id":"https://openalex.org/I99464096","display_name":"KU Leuven","ror":"https://ror.org/05f950310","country_code":"BE","type":"education","lineage":["https://openalex.org/I99464096"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Georges Gielen","raw_affiliation_strings":["KU Leuven,Dept. Electrical Engineering (ESAT- MICAS),Leuven,Belgium"],"affiliations":[{"raw_affiliation_string":"KU Leuven,Dept. Electrical Engineering (ESAT- MICAS),Leuven,Belgium","institution_ids":["https://openalex.org/I99464096"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I99464096"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.17523694,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12111","display_name":"Industrial Vision Systems and Defect Detection","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2209","display_name":"Industrial and Manufacturing Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.578105092048645},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5682583451271057},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.5564035773277283},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5068643689155579},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4945778548717499},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.47895413637161255},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.276813268661499},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20668300986289978},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10029616951942444}],"concepts":[{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.578105092048645},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5682583451271057},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.5564035773277283},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5068643689155579},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4945778548717499},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.47895413637161255},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.276813268661499},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20668300986289978},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10029616951942444}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/smacd65553.2025.11092178","is_oa":false,"landing_page_url":"https://doi.org/10.1109/smacd65553.2025.11092178","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD)","raw_type":"proceedings-article"},{"id":"pmh:oai:lirias2repo.kuleuven.be:20.500.12942/770921","is_oa":false,"landing_page_url":"https://lirias.kuleuven.be/handle/20.500.12942/770921","pdf_url":null,"source":{"id":"https://openalex.org/S4306401954","display_name":"Lirias (KU Leuven)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I99464096","host_organization_name":"KU Leuven","host_organization_lineage":["https://openalex.org/I99464096"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":"International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2025), Turkey, 7-10 July 2025","raw_type":"info:eu-repo/semantics/publishedVersion"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5699999928474426,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1486817281","https://openalex.org/W2024060531","https://openalex.org/W2132306241","https://openalex.org/W3033062045","https://openalex.org/W4200144194","https://openalex.org/W4286579628","https://openalex.org/W4320712918"],"related_works":["https://openalex.org/W4254560580","https://openalex.org/W2127167802","https://openalex.org/W2131559056","https://openalex.org/W2080984854","https://openalex.org/W2323083271","https://openalex.org/W2110962837","https://openalex.org/W4235748303","https://openalex.org/W4241196849","https://openalex.org/W2375192119","https://openalex.org/W3211653297"],"abstract_inverted_index":{"This":[0,85],"paper":[1],"shows":[2],"that":[3],"latent":[4],"defects":[5],"manifesting":[6],"as":[7,55],"pinholes":[8,102],"in":[9,24,30,66,90],"the":[10,25,42,67],"gate":[11],"oxide":[12],"of":[13,44],"transistors,":[14],"can":[15],"effectively":[16],"be":[17],"detected":[18],"by":[19],"inserting":[20],"extra":[21],"test":[22,36,39,62],"transistors":[23,40],"circuit":[26,51,68],"under":[27],"test,":[28],"working":[29],"tandem":[31],"with":[32,74,79],"a":[33,80],"neural":[34,82],"network":[35,83],"classifier.":[37,84],"The":[38,60],"have":[41],"functionality":[43],"applying":[45],"specific":[46],"voltage":[47],"levels":[48],"at":[49,71],"designated":[50],"nodes":[52,57],"and/or":[53],"acting":[54],"measurement":[56],"during":[58],"tests.":[59],"optimal":[61],"transistor":[63],"insertion":[64],"points":[65],"are":[69],"determined":[70],"design":[72],"time":[73],"simulated":[75],"annealing":[76],"optimization":[77],"integrated":[78],"feedback-providing":[81],"hybrid":[86],"approach":[87],"is":[88],"demonstrated":[89],"40nm":[91],"CMOS":[92],"for":[93,101],"two":[94],"opamp":[95],"circuits,":[96],"showing":[97],">90%":[98],"detection":[99],"coverage":[100],"below":[103],"85%":[104],"effective":[105],"thickness.":[106]},"counts_by_year":[],"updated_date":"2026-04-21T08:09:41.155169","created_date":"2025-10-10T00:00:00"}
