{"id":"https://openalex.org/W4245550140","doi":"https://doi.org/10.1109/simsym.2004.1299484","title":"Modelling SMIPS: a synthesisable asynchronous MIPS processor","display_name":"Modelling SMIPS: a synthesisable asynchronous MIPS processor","publication_year":2004,"publication_date":"2004-06-10","ids":{"openalex":"https://openalex.org/W4245550140","doi":"https://doi.org/10.1109/simsym.2004.1299484"},"language":"en","primary_location":{"id":"doi:10.1109/simsym.2004.1299484","is_oa":false,"landing_page_url":"https://doi.org/10.1109/simsym.2004.1299484","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"37th Annual Simulation Symposium, 2004. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5013950061","display_name":"Qing Zhang","orcid":"https://orcid.org/0009-0002-7142-7071"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Q. Zhang","raw_affiliation_strings":["School of Computer Science, University of Binningham, Birmingham, UK"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, University of Binningham, Birmingham, UK","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026385930","display_name":"Georgios Theodoropoulos","orcid":"https://orcid.org/0000-0002-7448-5886"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"G. Theodoropoulos","raw_affiliation_strings":["School of Computer Science, University of Binningham, Birmingham, UK"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, University of Binningham, Birmingham, UK","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5013950061"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.0532,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.78507112,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"4","issue":null,"first_page":"205","last_page":"212"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9799000024795532,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9799000024795532,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9789999723434448,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9783999919891357,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8986008167266846},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8073835372924805},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.706672191619873},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.5889627933502197},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5432461500167847},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.539788544178009},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.5294496417045593},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4740279018878937},{"id":"https://openalex.org/keywords/synchronizer","display_name":"Synchronizer","score":0.472788542509079},{"id":"https://openalex.org/keywords/asynchronous-system","display_name":"Asynchronous system","score":0.4697580337524414},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4638071060180664},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.45416077971458435},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.35359644889831543},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.29317817091941833},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.28882700204849243},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.152815580368042},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.12281480431556702},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10471925139427185},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09588029980659485}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8986008167266846},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8073835372924805},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.706672191619873},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.5889627933502197},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5432461500167847},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.539788544178009},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.5294496417045593},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4740279018878937},{"id":"https://openalex.org/C66727535","wikidata":"https://www.wikidata.org/wiki/Q7662199","display_name":"Synchronizer","level":2,"score":0.472788542509079},{"id":"https://openalex.org/C7923308","wikidata":"https://www.wikidata.org/wiki/Q4812211","display_name":"Asynchronous system","level":5,"score":0.4697580337524414},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4638071060180664},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.45416077971458435},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.35359644889831543},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.29317817091941833},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.28882700204849243},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.152815580368042},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.12281480431556702},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10471925139427185},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09588029980659485},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/simsym.2004.1299484","is_oa":false,"landing_page_url":"https://doi.org/10.1109/simsym.2004.1299484","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"37th Annual Simulation Symposium, 2004. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4699999988079071,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W136427456","https://openalex.org/W195696441","https://openalex.org/W1491226430","https://openalex.org/W1500293047","https://openalex.org/W1511688816","https://openalex.org/W1554812212","https://openalex.org/W1568175119","https://openalex.org/W1577703360","https://openalex.org/W1665361481","https://openalex.org/W1892184140","https://openalex.org/W1951899050","https://openalex.org/W1978308631","https://openalex.org/W2015855949","https://openalex.org/W2041279848","https://openalex.org/W2067044103","https://openalex.org/W2100382727","https://openalex.org/W2106783962","https://openalex.org/W2115264823","https://openalex.org/W2121155107","https://openalex.org/W2160823654","https://openalex.org/W2169332270","https://openalex.org/W2536760170","https://openalex.org/W4210886820","https://openalex.org/W6605501482","https://openalex.org/W6608036127","https://openalex.org/W6629326351","https://openalex.org/W6630623413","https://openalex.org/W6633282629","https://openalex.org/W6637168539","https://openalex.org/W6640693055","https://openalex.org/W6676995014","https://openalex.org/W6683394555"],"related_works":["https://openalex.org/W2095703739","https://openalex.org/W4312516786","https://openalex.org/W2109350679","https://openalex.org/W2378481815","https://openalex.org/W2110629111","https://openalex.org/W158833317","https://openalex.org/W2325117947","https://openalex.org/W628161287","https://openalex.org/W794031490","https://openalex.org/W2349909378"],"abstract_inverted_index":{"The":[0,67],"last":[1],"fifteen":[2],"years":[3],"have":[4],"witnessed":[5],"a":[6,37,46,54,91,99],"resurgence":[7],"of":[8,89],"interest":[9],"in":[10,97],"asynchronous":[11,64,93,101],"digital":[12],"design":[13,39,65],"techniques":[14,60],"as":[15,78],"they":[16],"promise":[17],"to":[18],"liberate":[19],"VLSI":[20],"systems":[21],"from":[22],"clock":[23],"skew":[24],"problems,":[25],"offer":[26],"the":[27,63,87],"potential":[28],"for":[29,56,62,81],"low":[30],"power":[31],"and":[32,35,58,105],"high":[33],"performance":[34],"encourage":[36],"modular":[38],"philosophy":[40],"which":[41],"makes":[42],"incremental":[43],"technological":[44],"migration":[45],"much":[47],"easier":[48],"task.":[49],"This":[50,84],"activity":[51],"has":[52],"revealed":[53],"need":[55],"modelling":[57,88],"simulation":[59],"suitable":[61,80],"style.":[66],"concurrent":[68],"process":[69],"algebra":[70],"communication":[71],"sequential":[72],"processes":[73],"(CSP)":[74],"is":[75],"increasingly":[76],"advocated":[77],"particularly":[79],"this":[82],"purpose.":[83],"paper":[85],"discusses":[86],"SAMIPS,":[90],"synthesisable":[92],"MIPS":[94],"processor":[95],"core,":[96],"Balsa,":[98],"CSP-based,":[100],"hardware":[102],"description":[103],"language":[104],"synthesis":[106],"tool.":[107]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
