{"id":"https://openalex.org/W2137302811","doi":"https://doi.org/10.1109/rtas.2008.6","title":"WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches","display_name":"WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches","publication_year":2008,"publication_date":"2008-04-01","ids":{"openalex":"https://openalex.org/W2137302811","doi":"https://doi.org/10.1109/rtas.2008.6","mag":"2137302811"},"language":"en","primary_location":{"id":"doi:10.1109/rtas.2008.6","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rtas.2008.6","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062127643","display_name":"Jun Yan","orcid":"https://orcid.org/0000-0003-1552-8003"},"institutions":[{"id":"https://openalex.org/I110378019","display_name":"Southern Illinois University Carbondale","ror":"https://ror.org/049kefs16","country_code":"US","type":"education","lineage":["https://openalex.org/I110378019","https://openalex.org/I2801502357"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jun Yan","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Southem Illinois University, Carbondale, Carbondale, IL, USA","Dept. of Electr. & Comput. Eng., Southern Illinois Univ. Carbondale, IL"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Southem Illinois University, Carbondale, Carbondale, IL, USA","institution_ids":["https://openalex.org/I110378019"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Southern Illinois Univ. Carbondale, IL","institution_ids":["https://openalex.org/I110378019"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5069960498","display_name":"Wei Zhang","orcid":"https://orcid.org/0000-0003-2615-2603"},"institutions":[{"id":"https://openalex.org/I110378019","display_name":"Southern Illinois University Carbondale","ror":"https://ror.org/049kefs16","country_code":"US","type":"education","lineage":["https://openalex.org/I110378019","https://openalex.org/I2801502357"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wei Zhang","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Southem Illinois University, Carbondale, Carbondale, IL, USA","Dept. of Electr. & Comput. Eng., Southern Illinois Univ. Carbondale, IL"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Southem Illinois University, Carbondale, Carbondale, IL, USA","institution_ids":["https://openalex.org/I110378019"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Southern Illinois Univ. Carbondale, IL","institution_ids":["https://openalex.org/I110378019"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5062127643"],"corresponding_institution_ids":["https://openalex.org/I110378019"],"apc_list":null,"apc_paid":null,"fwci":13.089,"has_fulltext":false,"cited_by_count":144,"citation_normalized_percentile":{"value":0.98933515,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"80","last_page":"89"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8955985307693481},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.8059945106506348},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.6433850526809692},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6012604832649231},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.5744220614433289},{"id":"https://openalex.org/keywords/bounding-overwatch","display_name":"Bounding overwatch","score":0.5492992401123047},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5352713465690613},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.5180463790893555},{"id":"https://openalex.org/keywords/control-flow","display_name":"Control flow","score":0.4924112558364868},{"id":"https://openalex.org/keywords/worst-case-execution-time","display_name":"Worst-case execution time","score":0.45820358395576477},{"id":"https://openalex.org/keywords/false-sharing","display_name":"False sharing","score":0.4468940198421478},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.437663197517395},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.43281030654907227},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4220581650733948},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3646894097328186},{"id":"https://openalex.org/keywords/execution-time","display_name":"Execution time","score":0.33757472038269043},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33542758226394653},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2818584442138672},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1594465672969818},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.10900753736495972}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8955985307693481},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.8059945106506348},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.6433850526809692},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6012604832649231},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.5744220614433289},{"id":"https://openalex.org/C63584917","wikidata":"https://www.wikidata.org/wiki/Q333286","display_name":"Bounding overwatch","level":2,"score":0.5492992401123047},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5352713465690613},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.5180463790893555},{"id":"https://openalex.org/C160191386","wikidata":"https://www.wikidata.org/wiki/Q868299","display_name":"Control flow","level":2,"score":0.4924112558364868},{"id":"https://openalex.org/C200130814","wikidata":"https://www.wikidata.org/wiki/Q362858","display_name":"Worst-case execution time","level":3,"score":0.45820358395576477},{"id":"https://openalex.org/C5165142","wikidata":"https://www.wikidata.org/wiki/Q5432732","display_name":"False sharing","level":5,"score":0.4468940198421478},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.437663197517395},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.43281030654907227},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4220581650733948},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3646894097328186},{"id":"https://openalex.org/C2989134064","wikidata":"https://www.wikidata.org/wiki/Q288510","display_name":"Execution time","level":2,"score":0.33757472038269043},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33542758226394653},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2818584442138672},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1594465672969818},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.10900753736495972},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/rtas.2008.6","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rtas.2008.6","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.521.4500","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.521.4500","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cecs.uci.edu/~papers/cpsweek08/papers/rtas08/2D.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6100000143051147,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W1499210710","https://openalex.org/W1533929374","https://openalex.org/W1563826489","https://openalex.org/W1826276806","https://openalex.org/W1916780844","https://openalex.org/W1943109230","https://openalex.org/W1976474972","https://openalex.org/W2076285066","https://openalex.org/W2119000119","https://openalex.org/W2123705102","https://openalex.org/W2134239125","https://openalex.org/W2138952175","https://openalex.org/W2140183411","https://openalex.org/W2146218445","https://openalex.org/W2148403317","https://openalex.org/W2149052625","https://openalex.org/W2159772935","https://openalex.org/W2162222856","https://openalex.org/W2163529295","https://openalex.org/W2243416539","https://openalex.org/W2545380179","https://openalex.org/W2911669905","https://openalex.org/W4285719527","https://openalex.org/W6638476580","https://openalex.org/W6644466695","https://openalex.org/W6669265065","https://openalex.org/W6676411099","https://openalex.org/W6683225327"],"related_works":["https://openalex.org/W2393506321","https://openalex.org/W1579918296","https://openalex.org/W146324612","https://openalex.org/W2079112005","https://openalex.org/W2083900817","https://openalex.org/W2130430041","https://openalex.org/W1997315696","https://openalex.org/W2133420723","https://openalex.org/W2047610444","https://openalex.org/W2137302811"],"abstract_inverted_index":{"Multi-core":[0],"chips":[1],"have":[2],"been":[3],"increasingly":[4],"adopted":[5],"by":[6,138,153,162],"microprocessor":[7],"industry.":[8],"For":[9],"real-time":[10],"systems":[11],"to":[12,24,43,73,95],"safely":[13],"harness":[14],"the":[15,27,44,55,60,75,97,107,124,130,144,160],"potential":[16],"of":[17,32,91,112,146],"multi-core":[18,36,65,82,150],"computing,":[19,66],"designers":[20],"must":[21],"be":[22,117],"able":[23],"accurately":[25],"obtain":[26],"worst-case":[28,76,98],"execution":[29],"time":[30],"(WCET)":[31],"applications":[33,147],"running":[34,80,148],"on":[35,81,106,149],"platforms,":[37],"which":[38,115],"is":[39,94,156],"very":[40],"challenging":[41],"due":[42],"possible":[45],"runtime":[46],"inter-core":[47],"interferences":[48,101],"in":[49],"using":[50],"shared":[51,56,85,133],"resources":[52],"such":[53],"as":[54],"L2":[57,86,134,166],"caches.":[58,88],"As":[59],"first":[61],"step":[62],"toward":[63],"time-predictable":[64],"this":[67],"paper":[68],"presents":[69],"a":[70],"novel":[71],"approach":[72,93,126,155],"bounding":[74],"performance":[77],"for":[78],"threads":[79,104],"processors":[83,151],"with":[84],"instruction":[87,99,135,141,167],"The":[89],"idea":[90],"our":[92,154],"compute":[96],"access":[100],"between":[102],"different":[103],"based":[105],"program":[108],"control":[109],"flow":[110],"information":[111],"each":[113],"thread,":[114],"can":[116,127],"statically":[118],"analyzed.":[119],"Our":[120],"experiments":[121],"indicate":[122],"that":[123],"proposed":[125],"reasonably":[128],"estimate":[129],"worst-":[131],"case":[132],"cache":[136],"misses":[137],"considering":[139],"inter-thread":[140],"conflicts.":[142],"Also,":[143],"WCET":[145],"estimated":[152],"much":[157],"better":[158],"than":[159],"estimation":[161],"simply":[163],"assuming":[164],"all":[165],"accesses":[168],"are":[169],"misses.":[170]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":3},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":6},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":12},{"year":2015,"cited_by_count":17},{"year":2014,"cited_by_count":20},{"year":2013,"cited_by_count":17},{"year":2012,"cited_by_count":14}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
