{"id":"https://openalex.org/W4231222038","doi":"https://doi.org/10.1109/recosoc.2014.6861350","title":"Reliably prototyping large SoCs using FPGA clusters","display_name":"Reliably prototyping large SoCs using FPGA clusters","publication_year":2014,"publication_date":"2014-05-01","ids":{"openalex":"https://openalex.org/W4231222038","doi":"https://doi.org/10.1109/recosoc.2014.6861350"},"language":"en","primary_location":{"id":"doi:10.1109/recosoc.2014.6861350","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2014.6861350","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103482964","display_name":"Paul Fox","orcid":null},"institutions":[{"id":"https://openalex.org/I241749","display_name":"University of Cambridge","ror":"https://ror.org/013meh722","country_code":"GB","type":"education","lineage":["https://openalex.org/I241749"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Paul J Fox","raw_affiliation_strings":["University of Cambridge, Cambridge, Cambridgeshire, GB"],"affiliations":[{"raw_affiliation_string":"University of Cambridge, Cambridge, Cambridgeshire, GB","institution_ids":["https://openalex.org/I241749"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086006620","display_name":"A. Theodore Markettos","orcid":"https://orcid.org/0009-0008-4411-2318"},"institutions":[{"id":"https://openalex.org/I241749","display_name":"University of Cambridge","ror":"https://ror.org/013meh722","country_code":"GB","type":"education","lineage":["https://openalex.org/I241749"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"A Theodore Markettos","raw_affiliation_strings":["University of Cambridge, Cambridge, Cambridgeshire, GB"],"affiliations":[{"raw_affiliation_string":"University of Cambridge, Cambridge, Cambridgeshire, GB","institution_ids":["https://openalex.org/I241749"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041439799","display_name":"Simon W. Moore","orcid":"https://orcid.org/0000-0002-2806-495X"},"institutions":[{"id":"https://openalex.org/I241749","display_name":"University of Cambridge","ror":"https://ror.org/013meh722","country_code":"GB","type":"education","lineage":["https://openalex.org/I241749"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Simon W Moore","raw_affiliation_strings":["University of Cambridge, Cambridge, Cambridgeshire, GB"],"affiliations":[{"raw_affiliation_string":"University of Cambridge, Cambridge, Cambridgeshire, GB","institution_ids":["https://openalex.org/I241749"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5103482964"],"corresponding_institution_ids":["https://openalex.org/I241749"],"apc_list":null,"apc_paid":null,"fwci":0.3448,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.71440968,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8671462535858154},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7539483904838562},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.693761944770813},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.589896559715271},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.5844724178314209},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.5120835304260254},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5051584839820862},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4922739565372467},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.4869033396244049},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.47160133719444275},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4421398937702179},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4263516962528229},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4141582250595093},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3302433490753174},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.1484731137752533},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1398376226425171},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07997217774391174}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8671462535858154},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7539483904838562},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.693761944770813},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.589896559715271},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.5844724178314209},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.5120835304260254},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5051584839820862},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4922739565372467},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4869033396244049},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.47160133719444275},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4421398937702179},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4263516962528229},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4141582250595093},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3302433490753174},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.1484731137752533},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1398376226425171},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07997217774391174},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/recosoc.2014.6861350","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2014.6861350","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G6375139917","display_name":null,"funder_award_id":"EP/G015783/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320306078","display_name":"U.S. Department of Defense","ror":"https://ror.org/0447fe631"},{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"},{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"},{"id":"https://openalex.org/F4320338294","display_name":"Air Force Research Laboratory","ror":"https://ror.org/02e2egq70"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1968712517","https://openalex.org/W1989299716","https://openalex.org/W2053105481","https://openalex.org/W2092736553","https://openalex.org/W2106982779","https://openalex.org/W2114691690","https://openalex.org/W2123184444","https://openalex.org/W2134736689","https://openalex.org/W2156360978"],"related_works":["https://openalex.org/W3010619501","https://openalex.org/W2161995522","https://openalex.org/W2135981148","https://openalex.org/W2043881088","https://openalex.org/W2390899382","https://openalex.org/W2388672758","https://openalex.org/W2065289416","https://openalex.org/W2754086592","https://openalex.org/W2144357574","https://openalex.org/W4230458348"],"abstract_inverted_index":{"Prototyping":[0],"large":[1],"SoCs":[2],"(Systems":[3],"on":[4,14,52],"Chip)":[5],"using":[6,32,37],"multiple":[7,33],"FPGAs":[8],"introduces":[9],"a":[10,29,44,53,66,69,73,97,101],"risk":[11],"of":[12,21,28,65,96,111],"errors":[13],"inter-FPGA":[15,57,112],"links.":[16,113],"This":[17],"raises":[18],"the":[19,26,78,94,108],"question":[20],"how":[22],"we":[23,103],"can":[24],"prove":[25],"correctness":[27],"SoC":[30,75],"prototyped":[31],"FPGAs.":[34],"We":[35],"propose":[36],"high-speed":[38],"serial":[39],"interconnect":[40,58],"between":[41,80],"FPGAs,":[42],"with":[43],"transparent":[45],"error":[46],"detection":[47],"and":[48,76,82,87],"correction":[49],"protocol":[50],"working":[51],"link-by-link":[54],"basis.":[55],"Our":[56],"has":[59],"an":[60],"interface":[61,71],"that":[62,64],"resembles":[63],"network-on-chip,":[67],"providing":[68],"consistent":[70],"to":[72],"prototype":[74],"masking":[77],"difference":[79],"on-chip":[81],"off-chip":[83],"interconnect.":[84],"Low-latency":[85],"communication":[86],"low":[88],"area":[89],"usage":[90],"are":[91],"favoured":[92],"at":[93],"expense":[95],"little":[98],"bandwidth":[99,110],"inefficiency,":[100],"trade-off":[102],"believe":[104],"is":[105],"appropriate":[106],"given":[107],"high":[109]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}