{"id":"https://openalex.org/W3006334812","doi":"https://doi.org/10.1109/reconfig48160.2019.8994798","title":"BFLOAT MLP Training Accelerator for FPGAs","display_name":"BFLOAT MLP Training Accelerator for FPGAs","publication_year":2019,"publication_date":"2019-12-01","ids":{"openalex":"https://openalex.org/W3006334812","doi":"https://doi.org/10.1109/reconfig48160.2019.8994798","mag":"3006334812"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig48160.2019.8994798","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig48160.2019.8994798","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054042334","display_name":"Andrei Hagiescu","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Andrei Hagiescu","raw_affiliation_strings":["Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082265695","display_name":"Martin Langhammer","orcid":"https://orcid.org/0000-0001-8206-2077"},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Martin Langhammer","raw_affiliation_strings":["Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010739346","display_name":"Bogdan Pasca","orcid":"https://orcid.org/0000-0002-5454-4375"},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Bogdan Pasca","raw_affiliation_strings":["Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055662480","display_name":"Philip Colangelo","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Philip Colangelo","raw_affiliation_strings":["Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085563125","display_name":"Jason Thong","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Jason Thong","raw_affiliation_strings":["Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038056451","display_name":"Niayesh Ilkhani","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Niayesh Ilkhani","raw_affiliation_strings":["Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5054042334"],"corresponding_institution_ids":["https://openalex.org/I4210158342"],"apc_list":null,"apc_paid":null,"fwci":0.2408,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.53991651,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8400281667709351},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7858284711837769},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5465393662452698},{"id":"https://openalex.org/keywords/floating-point","display_name":"Floating point","score":0.5275606513023376},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.464980810880661},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.4511722922325134},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4436858594417572},{"id":"https://openalex.org/keywords/point","display_name":"Point (geometry)","score":0.42364197969436646},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38417455554008484},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3467901349067688},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.20164549350738525},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18553799390792847}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8400281667709351},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7858284711837769},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5465393662452698},{"id":"https://openalex.org/C84211073","wikidata":"https://www.wikidata.org/wiki/Q117879","display_name":"Floating point","level":2,"score":0.5275606513023376},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.464980810880661},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.4511722922325134},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4436858594417572},{"id":"https://openalex.org/C28719098","wikidata":"https://www.wikidata.org/wiki/Q44946","display_name":"Point (geometry)","level":2,"score":0.42364197969436646},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38417455554008484},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3467901349067688},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.20164549350738525},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18553799390792847},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig48160.2019.8994798","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig48160.2019.8994798","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.47999998927116394,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1518881340","https://openalex.org/W1569512666","https://openalex.org/W2114508814","https://openalex.org/W2402704148","https://openalex.org/W2564531840","https://openalex.org/W2787839606","https://openalex.org/W2797533424","https://openalex.org/W2899644485","https://openalex.org/W3037484309","https://openalex.org/W4300232160","https://openalex.org/W6677192272","https://openalex.org/W6730868232","https://openalex.org/W6750597106","https://openalex.org/W6780234213"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W4200391368","https://openalex.org/W2355315220","https://openalex.org/W2210979487","https://openalex.org/W2074043759","https://openalex.org/W1967938402","https://openalex.org/W3028347934","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2185692674"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"the":[3,43,83,90],"architecture":[4,41],"of":[5,45,70,82,92],"a":[6,17,46,58,74],"FPGA-based":[7],"high-performance":[8,51],"training":[9,40,98],"accelerator":[10,15,67],"for":[11,49],"neural":[12,96],"networks.":[13],"Our":[14],"uses":[16],"hybrid":[18],"embedded":[19],"floating":[20],"point":[21],"and":[22,33,56,78],"soft":[23],"logic":[24],"approach":[25],"to":[26],"implement":[27],"truncated":[28],"floating-point":[29],"datapaths,":[30],"including":[31],"bfloat16":[32],"bfloat14.":[34],"The":[35,66],"proposed":[36],"multi-layer":[37],"perceptron":[38],"(MLP)":[39],"is":[42,68],"highlight":[44],"general":[47],"methodology":[48],"developing":[50],"accelerators":[52],"written":[53],"in":[54],"OpenCL":[55],"incorporating":[57],"systolic-array":[59],"GEMM":[60],"engine":[61],"with":[62],"off-chip":[63],"memory":[64],"interfaces.":[65],"capable":[69],"5":[71],"Tflops":[72],"on":[73],"mid-range":[75],"FPGA":[76],"device":[77],"achieves":[79],"over":[80],"90%":[81],"peak":[84],"efficiency":[85],"during":[86],"training,":[87],"thus":[88],"demonstrating":[89],"versatility":[91],"using":[93],"FPGAs":[94],"as":[95],"network":[97],"accelerators.":[99]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}