{"id":"https://openalex.org/W2910735017","doi":"https://doi.org/10.1109/reconfig.2018.8641699","title":"Exploring FPGA-specific Optimizations for Irregular OpenCL Applications","display_name":"Exploring FPGA-specific Optimizations for Irregular OpenCL Applications","publication_year":2018,"publication_date":"2018-12-01","ids":{"openalex":"https://openalex.org/W2910735017","doi":"https://doi.org/10.1109/reconfig.2018.8641699","mag":"2910735017"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2018.8641699","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2018.8641699","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050295731","display_name":"Mohamed W. Hassan","orcid":"https://orcid.org/0000-0002-7704-5376"},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Mohamed W. Hassan","raw_affiliation_strings":["Electrical & Computer Engineering, Virginia Tech, Blacksburg, VA, USA"],"affiliations":[{"raw_affiliation_string":"Electrical & Computer Engineering, Virginia Tech, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090060327","display_name":"Ahmed E. Helal","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ahmed E. Helal","raw_affiliation_strings":["Electrical & Computer Engineering, Virginia Tech, Blacksburg, VA, USA"],"affiliations":[{"raw_affiliation_string":"Electrical & Computer Engineering, Virginia Tech, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103964132","display_name":"Peter M. Athanas","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Peter M. Athanas","raw_affiliation_strings":["Electrical & Computer Engineering, Virginia Tech, Blacksburg, VA, USA"],"affiliations":[{"raw_affiliation_string":"Electrical & Computer Engineering, Virginia Tech, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058539554","display_name":"Wu-chun Feng","orcid":"https://orcid.org/0000-0002-6015-0727"},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wu-Chun Feng","raw_affiliation_strings":["Computer Science, Virginia Tech, Blacksburg, VA, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science, Virginia Tech, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5058341329","display_name":"Yasser Y. Hanafy","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yasser Y. Hanafy","raw_affiliation_strings":["Electrical & Computer Engineering, Virginia Tech, Blacksburg, VA, USA"],"affiliations":[{"raw_affiliation_string":"Electrical & Computer Engineering, Virginia Tech, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5050295731"],"corresponding_institution_ids":["https://openalex.org/I859038795"],"apc_list":null,"apc_paid":null,"fwci":2.5247,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.90112442,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8867315053939819},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7186363935470581},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5392393469810486},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5256052017211914},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5085235834121704},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.5075415372848511},{"id":"https://openalex.org/keywords/suite","display_name":"Suite","score":0.4890035390853882},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.4593501389026642},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4376639127731323},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3766719400882721},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1329243779182434}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8867315053939819},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7186363935470581},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5392393469810486},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5256052017211914},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5085235834121704},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.5075415372848511},{"id":"https://openalex.org/C79581498","wikidata":"https://www.wikidata.org/wiki/Q1367530","display_name":"Suite","level":2,"score":0.4890035390853882},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.4593501389026642},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4376639127731323},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3766719400882721},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1329243779182434},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C95457728","wikidata":"https://www.wikidata.org/wiki/Q309","display_name":"History","level":0,"score":0.0},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig.2018.8641699","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2018.8641699","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Decent work and economic growth","id":"https://metadata.un.org/sdg/8","score":0.5600000023841858}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W2000921084","https://openalex.org/W2006785118","https://openalex.org/W2021295531","https://openalex.org/W2022977427","https://openalex.org/W2078994750","https://openalex.org/W2166105886","https://openalex.org/W2175477959","https://openalex.org/W2264337508","https://openalex.org/W2317369144","https://openalex.org/W2359097465","https://openalex.org/W2365763746","https://openalex.org/W2472500612","https://openalex.org/W2620106252","https://openalex.org/W2763806130","https://openalex.org/W2771946537","https://openalex.org/W2807813421","https://openalex.org/W2885840893","https://openalex.org/W4236848524","https://openalex.org/W4252821989","https://openalex.org/W6693180885","https://openalex.org/W6707928459","https://openalex.org/W6744909076"],"related_works":["https://openalex.org/W2427933582","https://openalex.org/W2612099726","https://openalex.org/W1612076744","https://openalex.org/W2152074211","https://openalex.org/W2126857316","https://openalex.org/W2129019972","https://openalex.org/W3164085601","https://openalex.org/W1522032972","https://openalex.org/W2531450434","https://openalex.org/W2139962137"],"abstract_inverted_index":{"OpenCL":[0,25,77,87,150,171,211,222],"is":[1],"emerging":[2],"as":[3],"a":[4],"high-level":[5],"hardware":[6,21,51,141],"description":[7,22],"language":[8],"to":[9,30,37,48,62,110,124,145,154,215,219],"address":[10],"the":[11,40,67,82,112,116,127,137,147,156,165,190,207,220,225],"productivity":[12],"challenges":[13],"of":[14,66,115,149,158,169,209],"developing":[15],"applications":[16,88,212],"on":[17,92,136],"FPGAs.":[18],"Unlike":[19],"traditional":[20],"languages":[23],"(HDLs),":[24],"provides":[26],"an":[27],"abstract":[28],"interface":[29],"facilitate":[31],"high":[32],"productivity,":[33],"enabling":[34],"end":[35,108],"users":[36,109],"rapidly":[38],"describe":[39],"required":[41],"computations,":[42],"including":[43],"parallelism":[44],"and":[45,89,99,122,131,153,181,195],"data":[46],"movement,":[47],"create":[49],"custom":[50],"accelerators":[52,59],"for":[53,75,86],"their":[54],"applications.":[55,78],"However,":[56],"these":[57,118],"OpenCL-realized":[58],"are":[60,120,143],"unlikely":[61],"make":[63],"efficient":[64],"use":[65],"reconfigurable":[68],"fabric":[69],"without":[70],"adopting":[71],"FPGA-specific":[72,83,203],"optimizations,":[73],"particularly":[74],"irregular":[76,170,182,210],"Consequently,":[79],"we":[80,163],"explore":[81],"optimization":[84,94,104],"space":[85,105],"present":[90],"insights":[91],"which":[93,173],"techniques":[95],"improve":[96,206],"application":[97,138,151,199],"performance":[98,129,208],"resource":[100],"utilization.":[101],"Exploring":[102],"this":[103],"will":[106],"enable":[107],"harness":[111],"computational":[113],"potential":[114],"FPGA.While":[117],"optimizations":[119,204],"general":[121],"applicable":[123],"any":[125],"application,":[126],"expected":[128],"gain":[130],"resource-utilization":[132],"efficiency":[133],"vary":[134],"depending":[135],"characteristics.":[139],"Specifically,":[140],"profilers":[142],"used":[144],"analyze":[146],"limitations":[148],"kernels":[152,188],"guide":[155],"development":[157],"FPGA-optimized":[159],"implementations.":[160],"In":[161],"particular,":[162],"pursue":[164],"more":[166],"challenging":[167],"problem":[168],"applications,":[172],"suffer":[174],"from":[175,189,224],"workload":[176],"imbalance,":[177],"unpredictable":[178],"control":[179],"flow,":[180],"memory-access":[183],"patterns.":[184],"Experiments":[185],"using":[186],"representative":[187],"graph":[191],"traversal,":[192],"combinational":[193],"logic,":[194],"sparse":[196],"linear":[197],"algebra":[198],"domains":[200],"show":[201],"that":[202],"can":[205],"by":[213],"up":[214],"27-fold":[216],"in":[217],"comparison":[218],"architecture-agnostic":[221],"code":[223],"OpenDwarfs":[226],"benchmark":[227],"suite.":[228]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":3},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}