{"id":"https://openalex.org/W2785988832","doi":"https://doi.org/10.1109/reconfig.2017.8279802","title":"LinkBlaze: Efficient global data movement for FPGAs","display_name":"LinkBlaze: Efficient global data movement for FPGAs","publication_year":2017,"publication_date":"2017-12-01","ids":{"openalex":"https://openalex.org/W2785988832","doi":"https://doi.org/10.1109/reconfig.2017.8279802","mag":"2785988832"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2017.8279802","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2017.8279802","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036265450","display_name":"Pongstorn Maidee","orcid":"https://orcid.org/0000-0001-5838-1772"},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Pongstorn Maidee","raw_affiliation_strings":["Xilinx Research Labs., San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Xilinx Research Labs., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061071524","display_name":"Alireza Kaviani","orcid":"https://orcid.org/0000-0003-2229-4911"},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alireza Kaviani","raw_affiliation_strings":["Xilinx Research Labs., San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Xilinx Research Labs., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026923153","display_name":"Kevin Zeng","orcid":"https://orcid.org/0000-0002-6856-3489"},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kevin Zeng","raw_affiliation_strings":["Xilinx Research Labs., San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Xilinx Research Labs., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5036265450"],"corresponding_institution_ids":["https://openalex.org/I32923980"],"apc_list":null,"apc_paid":null,"fwci":1.2432,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.83433791,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9914000034332275,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8057888150215149},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7843464612960815},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.6142575144767761},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.5987395644187927},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5316221117973328},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5278083086013794},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5049610733985901},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4345315992832184},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.41999733448028564},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36576855182647705},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3374529778957367},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.20018211007118225},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10003361105918884}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8057888150215149},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7843464612960815},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.6142575144767761},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.5987395644187927},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5316221117973328},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5278083086013794},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5049610733985901},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4345315992832184},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.41999733448028564},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36576855182647705},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3374529778957367},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.20018211007118225},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10003361105918884},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig.2017.8279802","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2017.8279802","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1644436786","https://openalex.org/W2082295213","https://openalex.org/W2125662502","https://openalex.org/W2158565219","https://openalex.org/W2160610190","https://openalex.org/W2523891007"],"related_works":["https://openalex.org/W2110265185","https://openalex.org/W3146360095","https://openalex.org/W2127180614","https://openalex.org/W2167711148","https://openalex.org/W4235531327","https://openalex.org/W1603115038","https://openalex.org/W2177095534","https://openalex.org/W1964344619","https://openalex.org/W2163233359","https://openalex.org/W2184011203"],"abstract_inverted_index":{"FPGA":[0,66,111,183,248],"capacity":[1],"has":[2],"grown":[3],"rapidly":[4],"and":[5,20,110,123,134,180,230,239],"emerging":[6],"applications":[7],"comprise":[8],"a":[9,88,163,195,231],"large":[10],"number":[11,177],"of":[12,178],"compute":[13,48],"modules.":[14],"The":[15],"communication":[16],"among":[17],"these":[18,101],"modules":[19,49],"external":[21,84,219],"memory":[22,220],"will":[23,73],"cause":[24],"routing":[25],"congestion":[26],"in":[27,95,192,202],"fabric":[28,224],"interconnect.":[29],"This":[30,117],"problem":[31],"is":[32,41],"more":[33,214],"pronounced":[34],"with":[35,51],"process":[36],"scaling":[37],"since":[38],"the":[39,63,80,127,136,140,176,243,247],"technology":[40],"not":[42],"improving":[43],"wire":[44],"resistance.":[45],"High-speed":[46],"data":[47,77,93,165],"along":[50],"faster":[52],"local":[53],"storage":[54],"enable":[55],"efficient":[56,75],"kernels":[57],"running":[58],"at":[59,69],"500\u2013800":[60],"MHz":[61,146],"on":[62,129,139,148],"newer":[64],"devices.":[65],"system":[67],"performance":[68,147],"those":[70,159],"high":[71,170],"frequencies":[72],"require":[74],"global":[76,92,137,164],"movement":[78,94,166],"across":[79],"chip":[81],"from/to":[82],"an":[83,151,228],"memory.":[85],"We":[86,156,226],"propose":[87],"system-level":[89,190],"solution":[90,187,211,244],"for":[91,113,126,150,194,234,246],"FPGAs,":[96],"called":[97],"LinkBlaze,":[98],"to":[99,131,161,208,212,218,241],"address":[100],"issues.":[102],"LinkBlaze":[103],"leverages":[104],"both":[105],"general":[106],"Network-on-Chip":[107],"(NoC)":[108],"techniques":[109],"architecture":[112,229],"reducing":[114],"resource":[115],"usage.":[116],"work":[118],"explores":[119],"different":[120],"router":[121],"architectures":[122],"provides":[124],"insights":[125],"user":[128],"how":[130,207],"best":[132],"utilize":[133],"share":[135],"links":[138],"FPGA.":[141],"Our":[142,185,204],"results":[143,160,205],"indicate":[144,206],"640":[145],"Ultrascale+":[149,193],"optimized":[152],"3-port":[153],"soft":[154],"NoC.":[155],"further":[157],"extend":[158],"implement":[162,213],"overlay":[167,238],"operating":[168],"as":[169,171],"1":[172],"GHz,":[173],"by":[174],"restricting":[175],"clients":[179],"leveraging":[181],"flexible":[182],"placement.":[184],"proposed":[186,236],"enables":[188],"8GB/s":[189],"throughput":[191],"64-bit":[196],"instance,":[197],"while":[198],"using":[199,221],"underutilized":[200],"resources":[201],"FPGAs.":[203],"scale":[209],"our":[210,235],"than":[215],"52GB/s":[216],"access":[217],"2\u20133X":[222],"less":[223],"resources.":[225],"recommend":[227],"preferred":[232],"location":[233],"interconnect":[237],"intend":[240],"make":[242],"available":[245],"application":[249],"community.":[250]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}