{"id":"https://openalex.org/W2787225391","doi":"https://doi.org/10.1109/reconfig.2017.8279782","title":"Comparison of direct and switch-based inter-FPGA routing interconnect for multi-FPGA systems","display_name":"Comparison of direct and switch-based inter-FPGA routing interconnect for multi-FPGA systems","publication_year":2017,"publication_date":"2017-12-01","ids":{"openalex":"https://openalex.org/W2787225391","doi":"https://doi.org/10.1109/reconfig.2017.8279782","mag":"2787225391"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2017.8279782","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2017.8279782","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088890905","display_name":"Umer Farooq","orcid":"https://orcid.org/0000-0002-5220-4908"},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Umer Farooq","raw_affiliation_strings":["System on Chip (SoC) Department, UPMC University, Paris, France"],"affiliations":[{"raw_affiliation_string":"System on Chip (SoC) Department, UPMC University, Paris, France","institution_ids":["https://openalex.org/I39804081"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108405631","display_name":"Habib Mehrez","orcid":null},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Habib Mehrez","raw_affiliation_strings":["System on Chip (SoC) Department, UPMC University, Paris, France"],"affiliations":[{"raw_affiliation_string":"System on Chip (SoC) Department, UPMC University, Paris, France","institution_ids":["https://openalex.org/I39804081"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043625171","display_name":"Muhammad Khurram Bhatti","orcid":"https://orcid.org/0000-0002-1974-8268"},"institutions":[{"id":"https://openalex.org/I1323252656","display_name":"Information Technology University","ror":"https://ror.org/00ngv8j44","country_code":"PK","type":"education","lineage":["https://openalex.org/I1323252656"]}],"countries":["PK"],"is_corresponding":false,"raw_author_name":"Muhammad Khurram Bhatti","raw_affiliation_strings":["Electrical Engineering Department, Embedded Computing Lab ITU, Lahore, Pakistan"],"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, Embedded Computing Lab ITU, Lahore, Pakistan","institution_ids":["https://openalex.org/I1323252656"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5088890905"],"corresponding_institution_ids":["https://openalex.org/I39804081"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.19658436,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"11","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8451026678085327},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6892114877700806},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.6813827753067017},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.666114866733551},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6201369166374207},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.5717726945877075},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.5268046855926514},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.49864935874938965},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21877267956733704},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.12025147676467896},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10003849864006042}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8451026678085327},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6892114877700806},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.6813827753067017},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.666114866733551},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6201369166374207},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.5717726945877075},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.5268046855926514},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.49864935874938965},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21877267956733704},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.12025147676467896},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10003849864006042},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/reconfig.2017.8279782","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2017.8279782","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},{"id":"pmh:oai:sure.sunderland.ac.uk:16383","is_oa":false,"landing_page_url":"https://ieeexplore.ieee.org/document/8279782","pdf_url":null,"source":{"id":"https://openalex.org/S4306402295","display_name":"Sunderland Repository (University of Sunderland)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I5728261","host_organization_name":"University of Sunderland","host_organization_lineage":["https://openalex.org/I5728261"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"PeerReviewed"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.5299999713897705}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W564382181","https://openalex.org/W1992578807","https://openalex.org/W2063519198","https://openalex.org/W2105011467","https://openalex.org/W2109560035","https://openalex.org/W2127044295","https://openalex.org/W2161125053","https://openalex.org/W2275304190","https://openalex.org/W2541314013","https://openalex.org/W2558337280","https://openalex.org/W4206262605","https://openalex.org/W4232904085"],"related_works":["https://openalex.org/W2154523322","https://openalex.org/W2083200807","https://openalex.org/W1603137082","https://openalex.org/W2364195017","https://openalex.org/W2355430452","https://openalex.org/W2049983405","https://openalex.org/W2392315374","https://openalex.org/W1951195060","https://openalex.org/W3146360095","https://openalex.org/W2184011203"],"abstract_inverted_index":{"Prototyping":[0],"using":[1,86,104,149],"multi-FPGA":[2],"systems":[3],"offers":[4],"significant":[5],"advantages":[6],"over":[7],"simulation":[8],"and":[9,19,27,66,92,109,122,146,168],"emulation":[10],"based":[11],"pre-silicon":[12],"verification":[13],"techniques":[14],"in":[15,38,129],"terms":[16],"of":[17,30,41,90,107,132],"performance":[18,40],"real":[20],"world":[21],"testing":[22],"experience.":[23],"Inter-FPGA":[24],"routing":[25,57,64],"interconnect":[26,56,84,144,177],"the":[28,39,130,147,156],"quality":[29],"associated":[31],"tool":[32,65],"play":[33],"a":[34,50,61,87],"very":[35],"important":[36],"role":[37],"final":[42],"prototyped":[43,74],"design.":[44],"In":[45],"this":[46,123],"work,":[47],"we":[48],"present":[49,60],"detailed":[51],"comparison":[52,141],"between":[53,142],"four":[54,76,143],"inter-FPGA":[55],"topologies.":[58],"We":[59,136],"generic":[62],"inter-FPA":[63],"for":[67,98,118],"each":[68],"topology,":[69,162],"ten":[70],"large":[71,119],"benchmarks":[72],"are":[73],"on":[75,134,163],"different":[77],"FPGA":[78,100,120],"boards.":[79],"Experimental":[80],"results":[81,97,117],"show":[82],"that":[83],"topology":[85,103,148],"hybrid":[88,105],"combination":[89,106],"two":[91,151],"multipoint":[93],"tracks":[94,113],"gives":[95,114,155],"best":[96,115,157],"smaller":[99],"boards":[101,121],"while":[102],"switch-based":[108],"direct":[110,150],"multi":[111],"point":[112,152],"frequency":[116,124],"gain":[125],"increases":[126],"with":[127],"increase":[128],"number":[131],"FPGAs":[133],"board.":[135],"also":[137],"perform":[138],"execution":[139,159,171],"time":[140,172],"topologies":[145,178],"connections":[153],"only":[154],"overall":[158],"results.":[160],"This":[161],"average,":[164],"requires":[165],"12%,":[166],"82%,":[167],"70%":[169],"less":[170],"as":[173],"compared":[174],"to":[175],"other":[176],"under":[179],"consideration.":[180]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
