{"id":"https://openalex.org/W2786328319","doi":"https://doi.org/10.1109/reconfig.2017.8279780","title":"Biologically inspired hierarchical structure for self-repairing FPGAs","display_name":"Biologically inspired hierarchical structure for self-repairing FPGAs","publication_year":2017,"publication_date":"2017-12-01","ids":{"openalex":"https://openalex.org/W2786328319","doi":"https://doi.org/10.1109/reconfig.2017.8279780","mag":"2786328319"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2017.8279780","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2017.8279780","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019160373","display_name":"D.C. Keezer","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"David C. Keezer","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068895911","display_name":"Jingchi Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jingchi Yang","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia, USA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5019160373"],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":0.6759,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.71341826,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.7789819836616516},{"id":"https://openalex.org/keywords/triple-modular-redundancy","display_name":"Triple modular redundancy","score":0.7621873021125793},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.7273855805397034},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6945304870605469},{"id":"https://openalex.org/keywords/spare-part","display_name":"Spare part","score":0.6749922037124634},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.6680278182029724},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6675111651420593},{"id":"https://openalex.org/keywords/upgrade","display_name":"Upgrade","score":0.5581924915313721},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5369707345962524},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5012800693511963},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4760322868824005},{"id":"https://openalex.org/keywords/soft-error","display_name":"Soft error","score":0.46502116322517395},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.46103620529174805},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4237425923347473},{"id":"https://openalex.org/keywords/arithmetic-logic-unit","display_name":"Arithmetic logic unit","score":0.4112316370010376},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.36472541093826294},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3589508533477783},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.35054993629455566},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.22978457808494568},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1984865367412567},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18621009588241577},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.1074560284614563}],"concepts":[{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.7789819836616516},{"id":"https://openalex.org/C196371267","wikidata":"https://www.wikidata.org/wiki/Q3998979","display_name":"Triple modular redundancy","level":3,"score":0.7621873021125793},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.7273855805397034},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6945304870605469},{"id":"https://openalex.org/C194648553","wikidata":"https://www.wikidata.org/wiki/Q1364774","display_name":"Spare part","level":2,"score":0.6749922037124634},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.6680278182029724},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6675111651420593},{"id":"https://openalex.org/C2780615140","wikidata":"https://www.wikidata.org/wiki/Q920419","display_name":"Upgrade","level":2,"score":0.5581924915313721},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5369707345962524},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5012800693511963},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4760322868824005},{"id":"https://openalex.org/C154474529","wikidata":"https://www.wikidata.org/wiki/Q1658917","display_name":"Soft error","level":2,"score":0.46502116322517395},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.46103620529174805},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4237425923347473},{"id":"https://openalex.org/C100276221","wikidata":"https://www.wikidata.org/wiki/Q192903","display_name":"Arithmetic logic unit","level":2,"score":0.4112316370010376},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.36472541093826294},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3589508533477783},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.35054993629455566},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.22978457808494568},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1984865367412567},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18621009588241577},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.1074560284614563},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig.2017.8279780","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2017.8279780","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W181665514","https://openalex.org/W1551991454","https://openalex.org/W1555915743","https://openalex.org/W2026428156","https://openalex.org/W2040186632","https://openalex.org/W2124618076","https://openalex.org/W2150650385","https://openalex.org/W2160641632","https://openalex.org/W2343634302","https://openalex.org/W2531844514","https://openalex.org/W2725179571"],"related_works":["https://openalex.org/W2995137536","https://openalex.org/W1749592617","https://openalex.org/W2537369590","https://openalex.org/W2116473596","https://openalex.org/W2007710086","https://openalex.org/W2126481660","https://openalex.org/W2068711101","https://openalex.org/W3182233882","https://openalex.org/W2073572920","https://openalex.org/W2358210862"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3,111],"follow":[4],"the":[5,83,151],"lead":[6],"of":[7,106,153],"biology,":[8],"and":[9,26,30,32,54,71,81,108],"utilize":[10],"modular":[11],"redundancy":[12,28],"to":[13,48,65,79,131,150],"achieve":[14],"self-test":[15],"and,":[16],"especially,":[17],"self-repair":[18],"in":[19,87,135],"VLSI":[20],"systems.":[21],"We":[22,44,125,141],"first":[23,62],"review":[24],"dual-":[25],"tri-modular":[27],"(DMR":[29],"TMR)":[31],"show":[33,142],"why":[34],"these":[35,127],"well-established":[36],"techniques":[37],"alone":[38],"are":[39],"not":[40],"sufficient":[41],"for":[42],"self-repair.":[43],"introduce":[45],"two":[46],"enhancements":[47],"these:":[49],"(1)":[50],"distributed":[51],"BER":[52],"test,":[53],"(2)":[55],"self-diagnostics":[56],"with":[57],"autonomous":[58,104],"repair":[59,105],"logic.":[60],"The":[61,75],"is":[63,77],"used":[64,78],"distinguish":[66,80],"between":[67],"common":[68],"transient":[69],"errors":[70],"less-frequent":[72],"soft":[73,107],"faults.":[74],"second":[76],"isolate":[82],"failing":[84],"unit,":[85],"which":[86],"FPGAs":[88],"can":[89],"usually":[90],"be":[91],"healed":[92],"by":[93],"reprogramming":[94],"configuration":[95],"memory":[96],"using":[97],"dynamic":[98],"partial":[99],"reconfiguration.":[100],"To":[101],"enable":[102],"completely":[103],"hard":[109],"faults,":[110],"add":[112],"one":[113],"more":[114],"redundant":[115],"(spare)":[116],"unit":[117],"per":[118],"cell,":[119],"making":[120],"a":[121,136],"quadruple-redundant":[122],"system":[123,148],"(QMR*).":[124],"compare":[126],"methods":[128],"as":[129],"applied":[130],"several":[132],"benchmark":[133],"designs":[134],"28nm":[137],"Xilinx":[138],"Kintex-7":[139],"FPGA.":[140],"that":[143],"our":[144],"QMR*":[145],"approach":[146],"extends":[147],"reliability":[149],"order":[152],"centuries":[154],"(neglecting":[155],"wear-out":[156],"effects).":[157]},"counts_by_year":[{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}