{"id":"https://openalex.org/W4232563190","doi":"https://doi.org/10.1109/pcee.2004.42","title":"Loop Scheduling for Multithreaded Processors","display_name":"Loop Scheduling for Multithreaded Processors","publication_year":2005,"publication_date":"2005-04-06","ids":{"openalex":"https://openalex.org/W4232563190","doi":"https://doi.org/10.1109/pcee.2004.42"},"language":"en","primary_location":{"id":"doi:10.1109/pcee.2004.42","is_oa":false,"landing_page_url":"https://doi.org/10.1109/pcee.2004.42","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Parallel Computing in Electrical Engineering, International Conference on","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069074651","display_name":"G. Dimitriou","orcid":null},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"G. Dimitriou","raw_affiliation_strings":["Department of Computer Engineering, University of Thessally, Volos, Greece"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, University of Thessally, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059276291","display_name":"C. Polychronopoulos","orcid":null},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C. Polychronopoulos","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, USA","institution_ids":["https://openalex.org/I157725225"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5069074651"],"corresponding_institution_ids":["https://openalex.org/I145722265"],"apc_list":null,"apc_paid":null,"fwci":0.26536691,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.67991974,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"361","last_page":"366"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9955000281333923,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8693080544471741},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.846972644329071},{"id":"https://openalex.org/keywords/software-pipelining","display_name":"Software pipelining","score":0.7771892547607422},{"id":"https://openalex.org/keywords/loop-tiling","display_name":"Loop tiling","score":0.6427018642425537},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.6034609079360962},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.578011155128479},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5485424399375916},{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.5172649025917053},{"id":"https://openalex.org/keywords/uniprocessor-system","display_name":"Uniprocessor system","score":0.4875878691673279},{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.4770633280277252},{"id":"https://openalex.org/keywords/simultaneous-multithreading","display_name":"Simultaneous multithreading","score":0.43668070435523987},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.3004786968231201},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.27149420976638794},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.23794078826904297},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.19554799795150757}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8693080544471741},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.846972644329071},{"id":"https://openalex.org/C188854837","wikidata":"https://www.wikidata.org/wiki/Q268469","display_name":"Software pipelining","level":3,"score":0.7771892547607422},{"id":"https://openalex.org/C11799548","wikidata":"https://www.wikidata.org/wiki/Q6675847","display_name":"Loop tiling","level":3,"score":0.6427018642425537},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.6034609079360962},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.578011155128479},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5485424399375916},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.5172649025917053},{"id":"https://openalex.org/C79189994","wikidata":"https://www.wikidata.org/wiki/Q3488021","display_name":"Uniprocessor system","level":3,"score":0.4875878691673279},{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.4770633280277252},{"id":"https://openalex.org/C85717602","wikidata":"https://www.wikidata.org/wiki/Q82178","display_name":"Simultaneous multithreading","level":4,"score":0.43668070435523987},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.3004786968231201},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.27149420976638794},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.23794078826904297},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.19554799795150757},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/pcee.2004.42","is_oa":false,"landing_page_url":"https://doi.org/10.1109/pcee.2004.42","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Parallel Computing in Electrical Engineering, International Conference on","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"},{"id":"https://openalex.org/F4320311089","display_name":"National Security Agency","ror":"https://ror.org/0047bvr32"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W90084074","https://openalex.org/W121029738","https://openalex.org/W129816012","https://openalex.org/W1524877046","https://openalex.org/W1601753226","https://openalex.org/W1920053666","https://openalex.org/W1990199656","https://openalex.org/W2063255488","https://openalex.org/W2095703459","https://openalex.org/W2098688018","https://openalex.org/W2108200978","https://openalex.org/W2150547581","https://openalex.org/W2296006986","https://openalex.org/W2532467869","https://openalex.org/W2971181817","https://openalex.org/W3142147837","https://openalex.org/W3143103159","https://openalex.org/W4245971498","https://openalex.org/W4247317410","https://openalex.org/W6635987275"],"related_works":["https://openalex.org/W4247312607","https://openalex.org/W2042766074","https://openalex.org/W4240874773","https://openalex.org/W2083264194","https://openalex.org/W2092462759","https://openalex.org/W2135234700","https://openalex.org/W2125951114","https://openalex.org/W217231416","https://openalex.org/W2377042343","https://openalex.org/W1603958403"],"abstract_inverted_index":{"The":[0],"presence":[1],"of":[2,99,119,138],"multiple":[3],"active":[4],"threads":[5],"on":[6,49,87,104,130,142],"the":[7,50,63],"same":[8],"processor":[9],"can":[10,19],"mask":[11],"latency":[12],"by":[13,61],"rapid":[14],"context":[15],"switching,":[16],"but":[17],"it":[18],"adversely":[20],"affect":[21],"performance":[22],"due":[23],"to":[24,72,121,125,140],"competition":[25],"for":[26,43,54,79,96],"shared":[27],"datapath":[28],"resources.":[29],"In":[30],"this":[31],"paper":[32],"we":[33],"present":[34],"Macro":[35],"Software":[36],"Pipelining":[37],"(MSWP),":[38],"a":[39,73,88,105,136,144],"loop":[40,51,55,59,64],"scheduling":[41],"technique":[42],"multithreaded":[44,106],"processors,":[45],"which":[46],"is":[47,84],"based":[48],"distribution":[52],"transformation":[53],"pipelining.":[56],"MSWP":[57,83,103],"constructs":[58],"schedules":[60,129],"partitioning":[62],"body":[65],"into":[66],"tasks":[67],"and":[68,92,113,135],"assigning":[69],"each":[70],"task":[71],"thread":[74],"that":[75,80],"executes":[76],"all":[77],"iterations":[78],"particular":[81],"task.":[82],"applied":[85],"top-down":[86],"hierarchical":[89],"program":[90],"representation,":[91],"utilizes":[93],"thread-level":[94],"speculation":[95],"maximal":[97],"exploitation":[98],"parallelism.":[100],"We":[101,116],"tested":[102],"architectural":[107],"model,":[108],"Coral":[109],"2000,":[110],"using":[111],"synthetic":[112],"SPEC":[114],"benchmarks.":[115],"obtained":[117],"speedups":[118],"up":[120,139],"30%":[122],"with":[123,132],"respect":[124],"highly":[126,145],"optimized":[127],"superblock-based":[128],"loops":[131],"unpredictable":[133],"branches,":[134],"speedup":[137],"25%":[141],"perl,":[143],"sequential":[146],"SPEC95":[147],"integer":[148],"benchmark.":[149]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}