{"id":"https://openalex.org/W4417403303","doi":"https://doi.org/10.1109/pact65351.2025.00033","title":"Energy-Efficient Acceleration of Hash-Based Post-Quantum Cryptographic Schemes on Embedded Spatial Architectures","display_name":"Energy-Efficient Acceleration of Hash-Based Post-Quantum Cryptographic Schemes on Embedded Spatial Architectures","publication_year":2025,"publication_date":"2025-11-03","ids":{"openalex":"https://openalex.org/W4417403303","doi":"https://doi.org/10.1109/pact65351.2025.00033"},"language":null,"primary_location":{"id":"doi:10.1109/pact65351.2025.00033","is_oa":false,"landing_page_url":"https://doi.org/10.1109/pact65351.2025.00033","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 34th International Conference on Parallel Architectures and Compilation Techniques (PACT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019129523","display_name":"Yanze Wu","orcid":"https://orcid.org/0000-0001-7113-3511"},"institutions":[{"id":"https://openalex.org/I162714631","display_name":"George Mason University","ror":"https://ror.org/02jqj7156","country_code":"US","type":"education","lineage":["https://openalex.org/I162714631"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Yanze Wu","raw_affiliation_strings":["George Mason University,Cyber Security Engineering Department,Fairfax,US"],"affiliations":[{"raw_affiliation_string":"George Mason University,Cyber Security Engineering Department,Fairfax,US","institution_ids":["https://openalex.org/I162714631"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077280198","display_name":"Md Tanvir Arafin","orcid":"https://orcid.org/0000-0002-5179-5216"},"institutions":[{"id":"https://openalex.org/I162714631","display_name":"George Mason University","ror":"https://ror.org/02jqj7156","country_code":"US","type":"education","lineage":["https://openalex.org/I162714631"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Md Tanvir Arafin","raw_affiliation_strings":["George Mason University,Cyber Security Engineering Department,Fairfax,US"],"affiliations":[{"raw_affiliation_string":"George Mason University,Cyber Security Engineering Department,Fairfax,US","institution_ids":["https://openalex.org/I162714631"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5019129523"],"corresponding_institution_ids":["https://openalex.org/I162714631"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.21114314,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"270","last_page":"280"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.8848000168800354,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.8848000168800354,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.03139999881386757,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.024700000882148743,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.7078999876976013},{"id":"https://openalex.org/keywords/acceleration","display_name":"Acceleration","score":0.6657999753952026},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5774000287055969},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.4975999891757965},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.445499986410141},{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.4316999912261963},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.4106999933719635}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7386000156402588},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.7078999876976013},{"id":"https://openalex.org/C117896860","wikidata":"https://www.wikidata.org/wiki/Q11376","display_name":"Acceleration","level":2,"score":0.6657999753952026},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5774000287055969},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.4975999891757965},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.445499986410141},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.4316999912261963},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.4106999933719635},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.3873000144958496},{"id":"https://openalex.org/C2779696439","wikidata":"https://www.wikidata.org/wiki/Q7512811","display_name":"Signature (topology)","level":2,"score":0.383899986743927},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37560001015663147},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.366100013256073},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36579999327659607},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.35089999437332153},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.34880000352859497},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.3292999863624573},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.3221000134944916},{"id":"https://openalex.org/C2989134064","wikidata":"https://www.wikidata.org/wiki/Q288510","display_name":"Execution time","level":2,"score":0.30709999799728394},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.30550000071525574},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3010999858379364},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.27889999747276306},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.2732999920845032},{"id":"https://openalex.org/C3020431745","wikidata":"https://www.wikidata.org/wiki/Q25325220","display_name":"Many core","level":2,"score":0.2612999975681305}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/pact65351.2025.00033","is_oa":false,"landing_page_url":"https://doi.org/10.1109/pact65351.2025.00033","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 34th International Conference on Parallel Architectures and Compilation Techniques (PACT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1566345534","https://openalex.org/W1598984807","https://openalex.org/W2015880590","https://openalex.org/W2074594718","https://openalex.org/W2117362057","https://openalex.org/W2131489800","https://openalex.org/W2155690458","https://openalex.org/W2591922920","https://openalex.org/W2806487405","https://openalex.org/W2912890068","https://openalex.org/W3019560945","https://openalex.org/W3036521249","https://openalex.org/W3113636917","https://openalex.org/W3135242540","https://openalex.org/W3202332328","https://openalex.org/W4293731904","https://openalex.org/W4304140716","https://openalex.org/W4313476770","https://openalex.org/W4319870545","https://openalex.org/W4321637087","https://openalex.org/W4386710216","https://openalex.org/W4386763982","https://openalex.org/W4388214721","https://openalex.org/W4388464410","https://openalex.org/W4389162879","https://openalex.org/W4391455288","https://openalex.org/W4401017906"],"related_works":[],"abstract_inverted_index":{"This":[0,166],"work":[1],"introduces":[2],"AXIOS,":[3],"a":[4,83,92,155],"novel":[5],"spatial":[6,28,147],"architecture":[7],"for":[8,34,42],"accelerating":[9],"hash-based":[10,21,65,141],"post-quantum":[11],"cryptography":[12],"(PQC)":[13,66],"primitives.":[14],"AXIOS":[15,45,69,107],"demonstrates":[16,75],"that":[17,30],"structural":[18],"regularities":[19],"in":[20,63,80,87,116,144],"algorithms":[22],"can":[23],"be":[24],"efficiently":[25],"mapped":[26],"to":[27,91,158],"accelerators":[29],"support":[31,159],"FPGA-based":[32],"programming":[33],"granular":[35],"control":[36],"and":[37,82,169],"coarse-grained":[38],"reconfigurable":[39],"arrays":[40],"(CGRA)":[41],"repeated":[43],"tasks.":[44],"selects":[46],"the":[47,52,110,134,164],"key":[48],"generation":[49],"task":[50],"of":[51,113,118,139],"eXtended":[53],"Markle":[54],"Signature":[55],"Scheme":[56],"(XMSS),":[57],"which":[58],"embodies":[59],"critical":[60],"implementation":[61,70,94,138],"challenges":[62],"modern":[64],"algorithms.":[67],"The":[68],"on":[71,95,121],"AMD\u2019s":[72],"VCK190":[73],"platform":[74],"an":[76,122,126,145],"$8.54":[77],"\\times$":[78,85],"improvement":[79,86],"runtime":[81],"$71.65":[84],"energy":[88],"efficiency":[89],"compared":[90],"benchmark":[93],"Intel\u2019s":[96],"Core":[97],"$\\mathbf{i":[98],"9":[99,103],"-":[100],"1":[101],"4":[102],"0":[104,105],"K}$.":[106],"also":[108],"breaks":[109],"current":[111],"record":[112],"XMSS":[114],"acceleration":[115],"terms":[117],"execution":[119],"time":[120],"embedded":[123,146],"SoC":[124],"or":[125],"FPGA":[127],"platform.":[128],"To":[129],"our":[130],"knowledge,":[131],"this":[132,151],"is":[133,154],"first":[135],"efficient":[136],"hardware":[137],"compute-intensive":[140,160],"PQC":[142,161],"schemes":[143],"architecture.":[148],"Albeit":[149],"complex,":[150],"FPGA+CGRA-based":[152],"design":[153],"promising":[156],"step":[157],"applications":[162],"at":[163,175],"edge.":[165],"work\u2019s":[167],"code":[168],"experimental":[170],"artifacts":[171],"are":[172],"publicly":[173],"available":[174],"https://github.com/SPIRE-GMU/AXIOS.":[176]},"counts_by_year":[],"updated_date":"2026-04-09T08:11:56.329763","created_date":"2025-12-16T00:00:00"}