{"id":"https://openalex.org/W4417403163","doi":"https://doi.org/10.1109/pact65351.2025.00018","title":"Exploring Memory Tiering Systems in the CXL Era via FPGA-based Emulation and Device-Side Management","display_name":"Exploring Memory Tiering Systems in the CXL Era via FPGA-based Emulation and Device-Side Management","publication_year":2025,"publication_date":"2025-11-03","ids":{"openalex":"https://openalex.org/W4417403163","doi":"https://doi.org/10.1109/pact65351.2025.00018"},"language":null,"primary_location":{"id":"doi:10.1109/pact65351.2025.00018","is_oa":false,"landing_page_url":"https://doi.org/10.1109/pact65351.2025.00018","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 34th International Conference on Parallel Architectures and Compilation Techniques (PACT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102981535","display_name":"Yiqi Chen","orcid":"https://orcid.org/0009-0003-5644-4719"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Yiqi Chen","raw_affiliation_strings":["School of Integrated Circuits"],"affiliations":[{"raw_affiliation_string":"School of Integrated Circuits","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020237745","display_name":"Xiping Dong","orcid":"https://orcid.org/0009-0001-8720-5804"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Xiping Dong","raw_affiliation_strings":["School of Integrated Circuits"],"affiliations":[{"raw_affiliation_string":"School of Integrated Circuits","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101461597","display_name":"Zhe Zhou","orcid":"https://orcid.org/0009-0008-9701-4607"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Zhe Zhou","raw_affiliation_strings":["School of Integrated Circuits"],"affiliations":[{"raw_affiliation_string":"School of Integrated Circuits","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100434557","display_name":"Zhao Wang","orcid":"https://orcid.org/0000-0003-0147-6054"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Zhao Wang","raw_affiliation_strings":["School of Integrated Circuits"],"affiliations":[{"raw_affiliation_string":"School of Integrated Circuits","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100436779","display_name":"Jie Zhang","orcid":"https://orcid.org/0000-0002-6299-4683"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jie Zhang","raw_affiliation_strings":["Peking University,School of Computer Science"],"affiliations":[{"raw_affiliation_string":"Peking University,School of Computer Science","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101850376","display_name":"Guangyu Sun","orcid":"https://orcid.org/0000-0001-6436-0820"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Guangyu Sun","raw_affiliation_strings":["School of Integrated Circuits"],"affiliations":[{"raw_affiliation_string":"School of Integrated Circuits","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5102981535"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.43314734,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"71","last_page":"83"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.664900004863739,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.664900004863739,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10101","display_name":"Cloud Computing and Resource Management","score":0.058400001376867294,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.04529999941587448,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.7160999774932861},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.637499988079071},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.5958999991416931},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.5633999705314636},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.5612999796867371},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.5205000042915344},{"id":"https://openalex.org/keywords/extended-memory","display_name":"Extended memory","score":0.5120000243186951},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.42500001192092896},{"id":"https://openalex.org/keywords/physical-address","display_name":"Physical address","score":0.42410001158714294},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.42309999465942383}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8091999888420105},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.7160999774932861},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.637499988079071},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6078000068664551},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.5958999991416931},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.5633999705314636},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.5612999796867371},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.5205000042915344},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.5120000243186951},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.42500001192092896},{"id":"https://openalex.org/C41036726","wikidata":"https://www.wikidata.org/wiki/Q844824","display_name":"Physical address","level":3,"score":0.42410001158714294},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.42309999465942383},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4068000018596649},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.4025999903678894},{"id":"https://openalex.org/C18131444","wikidata":"https://www.wikidata.org/wiki/Q163585","display_name":"Memory protection","level":5,"score":0.39419999718666077},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.38589999079704285},{"id":"https://openalex.org/C76399640","wikidata":"https://www.wikidata.org/wiki/Q189401","display_name":"Virtual memory","level":4,"score":0.3799000084400177},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.3695000112056732},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3582000136375427},{"id":"https://openalex.org/C53838383","wikidata":"https://www.wikidata.org/wiki/Q541148","display_name":"Conventional memory","level":5,"score":0.3564000129699707},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.3483000099658966},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.3433000147342682},{"id":"https://openalex.org/C39528615","wikidata":"https://www.wikidata.org/wiki/Q1229610","display_name":"Distributed shared memory","level":5,"score":0.3375999927520752},{"id":"https://openalex.org/C152890283","wikidata":"https://www.wikidata.org/wiki/Q4129922","display_name":"Computing with Memory","level":5,"score":0.32839998602867126},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.31859999895095825},{"id":"https://openalex.org/C144240696","wikidata":"https://www.wikidata.org/wiki/Q367204","display_name":"Address space","level":2,"score":0.3156999945640564},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.2883000075817108},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.28139999508857727},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.2732999920845032},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.26809999346733093},{"id":"https://openalex.org/C47487241","wikidata":"https://www.wikidata.org/wiki/Q5227230","display_name":"Data access","level":2,"score":0.26510000228881836},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.26330000162124634},{"id":"https://openalex.org/C147358964","wikidata":"https://www.wikidata.org/wiki/Q1200992","display_name":"Abstraction layer","level":3,"score":0.25380000472068787},{"id":"https://openalex.org/C64142963","wikidata":"https://www.wikidata.org/wiki/Q1153902","display_name":"Phase-change memory","level":3,"score":0.25119999051094055}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/pact65351.2025.00018","is_oa":false,"landing_page_url":"https://doi.org/10.1109/pact65351.2025.00018","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 34th International Conference on Parallel Architectures and Compilation Techniques (PACT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320337504","display_name":"Research and Development","ror":"https://ror.org/027s68j25"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":39,"referenced_works":["https://openalex.org/W1993089791","https://openalex.org/W2013626513","https://openalex.org/W2080234606","https://openalex.org/W2141710443","https://openalex.org/W2292369231","https://openalex.org/W2340522713","https://openalex.org/W2612798083","https://openalex.org/W2614002281","https://openalex.org/W2742513757","https://openalex.org/W2798337732","https://openalex.org/W2809837139","https://openalex.org/W2891584720","https://openalex.org/W2904353462","https://openalex.org/W2922365623","https://openalex.org/W2934584470","https://openalex.org/W2953358830","https://openalex.org/W2985838475","https://openalex.org/W3001684375","https://openalex.org/W3010830594","https://openalex.org/W3109760540","https://openalex.org/W3157864729","https://openalex.org/W3173984363","https://openalex.org/W3206341493","https://openalex.org/W4214645260","https://openalex.org/W4220750849","https://openalex.org/W4232557115","https://openalex.org/W4280587521","https://openalex.org/W4315630617","https://openalex.org/W4317033481","https://openalex.org/W4318541517","https://openalex.org/W4327930415","https://openalex.org/W4327930439","https://openalex.org/W4360831822","https://openalex.org/W4361194512","https://openalex.org/W4372263020","https://openalex.org/W4387302703","https://openalex.org/W4387321556","https://openalex.org/W4388581411","https://openalex.org/W4399677840"],"related_works":[],"abstract_inverted_index":{"The":[0],"Compute":[1],"Express":[2],"Link":[3],"(CXL)":[4],"technology":[5],"facilitates":[6],"the":[7,125,153,183,192,213,233],"extension":[8],"of":[9,127,155],"CPU":[10,25,193],"memory":[11,22,37,52,58,80,91,130,138,160,177,206,228,249],"through":[12],"byte-addressable":[13],"SerDes":[14],"links":[15],"and":[16,33,69,83,102,105,148,158,166,194,201],"cascaded":[17],"switches,":[18],"creating":[19],"complex":[20],"heterogeneous":[21,57,227],"systems":[23,93,162],"where":[24],"access":[26],"to":[27,95,123,135,204,232,240],"various":[28,128],"endpoints":[29],"differs":[30],"in":[31,45,76],"latency":[32,147],"bandwidth.":[34,149],"Effective":[35],"tiered":[36,79],"management":[38,81,229],"is":[39],"essential":[40],"for":[41,55],"optimizing":[42],"system":[43,54,179],"performance":[44,126,154,224,245],"such":[46,65],"systems.":[47],"However,":[48],"designing":[49],"an":[50,188],"effective":[51],"tiering":[53,92,161,178,250],"CXL-extended":[56],"faces":[59],"challenges:":[60],"1)":[61],"Existing":[62],"evaluation":[63],"methods,":[64],"as":[66],"NUMA-based":[67],"emulation":[68,116],"full-system":[70],"simulations":[71],"like":[72],"GEM5,":[73],"are":[74],"limited":[75],"assessing":[77],"hardware-based":[78],"solutions":[82],"handling":[84],"real-world":[85,217],"workloads":[86],"at":[87],"scale.":[88],"2)":[89],"Previous":[90],"struggle":[94],"simultaneously":[96],"achieve":[97],"high":[98,103,164,223],"resolution,":[99],"low":[100],"overhead,":[101],"flexibility":[104],"compatibility.":[106],"In":[107],"this":[108],"study,":[109],"we":[110,171],"first":[111],"introduce":[112],"HeteroBox,":[113,170],"a":[114,137,175,236],"configurable":[115],"platform":[117],"that":[118,180,220],"leverages":[119],"real":[120],"CXL-enabled":[121],"FPGAs":[122],"emulate":[124],"CXL":[129],"architectures.":[131],"HeteroBox":[132,150],"allows":[133],"one":[134],"configure":[136],"space":[139],"with":[140,163,216],"multiple":[141],"regions,":[142],"each":[143],"exhibiting":[144],"distinct":[145],"CPU-access":[146],"helps":[151],"assess":[152],"both":[156],"software-managed":[157],"hardware-managed":[159,176],"efficiency":[165],"fidelity.":[167],"Based":[168],"on":[169,182],"further":[172],"propose":[173],"HeteroMem,":[174],"operates":[181],"device":[184,195],"side.":[185],"HeteroMem":[186,221],"creates":[187],"abstraction":[189],"layer":[190],"between":[191],"memory,":[196],"effectively":[197],"monitoring":[198],"data":[199,203],"usage":[200],"migrating":[202],"faster":[205],"tiers,":[207],"thus":[208],"hiding":[209],"device-side":[210],"heterogeneity":[211],"from":[212],"CPU.":[214],"Evaluations":[215],"applications":[218],"show":[219],"delivers":[222],"while":[225],"keeping":[226],"fully":[230],"transparent":[231],"CPU,":[234],"achieving":[235],"$\\mathbf{5.":[237],"1}$":[238],"%":[239,244],"$\\mathbf{1":[241],"6.":[242],"2}$":[243],"improvement":[246],"over":[247],"existing":[248],"solutions.":[251]},"counts_by_year":[],"updated_date":"2026-04-09T08:11:56.329763","created_date":"2025-12-16T00:00:00"}