{"id":"https://openalex.org/W2294253319","doi":"https://doi.org/10.1109/pact.2015.58","title":"Energy-Efficient Hybrid DRAM/NVM Main Memory","display_name":"Energy-Efficient Hybrid DRAM/NVM Main Memory","publication_year":2015,"publication_date":"2015-10-01","ids":{"openalex":"https://openalex.org/W2294253319","doi":"https://doi.org/10.1109/pact.2015.58","mag":"2294253319"},"language":"en","primary_location":{"id":"doi:10.1109/pact.2015.58","is_oa":false,"landing_page_url":"https://doi.org/10.1109/pact.2015.58","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 International Conference on Parallel Architecture and Compilation (PACT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025790744","display_name":"Ahmad Hassan","orcid":"https://orcid.org/0009-0006-6841-3364"},"institutions":[{"id":"https://openalex.org/I4210133614","display_name":"Systems, Applications & Products in Data Processing (United Kingdom)","ror":"https://ror.org/04k7gd586","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210132444","https://openalex.org/I4210133614"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Ahmad Hassan","raw_affiliation_strings":["SAP Labs Belfast, United Kingdom"],"affiliations":[{"raw_affiliation_string":"SAP Labs Belfast, United Kingdom","institution_ids":["https://openalex.org/I4210133614"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086758775","display_name":"Hans Vandierendonck","orcid":"https://orcid.org/0000-0001-5868-9259"},"institutions":[{"id":"https://openalex.org/I126231945","display_name":"Queen's University Belfast","ror":"https://ror.org/00hswnk62","country_code":"GB","type":"education","lineage":["https://openalex.org/I126231945"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Hans Vandierendonck","raw_affiliation_strings":["Queen's University of Belfast Belfast, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Queen's University of Belfast Belfast, United Kingdom","institution_ids":["https://openalex.org/I126231945"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005410613","display_name":"Dimitrios S. Nikolopoulos","orcid":"https://orcid.org/0000-0003-0217-8307"},"institutions":[{"id":"https://openalex.org/I126231945","display_name":"Queen's University Belfast","ror":"https://ror.org/00hswnk62","country_code":"GB","type":"education","lineage":["https://openalex.org/I126231945"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Dimitrios S. Nikolopoulos","raw_affiliation_strings":["Queen's University of Belfast Belfast, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Queen's University of Belfast Belfast, United Kingdom","institution_ids":["https://openalex.org/I126231945"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5025790744"],"corresponding_institution_ids":["https://openalex.org/I4210133614"],"apc_list":null,"apc_paid":null,"fwci":2.5839,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.90114445,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"492","last_page":"493"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.9014298915863037},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6966955661773682},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6031164526939392},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.5912623405456543},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.5239964723587036},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.483051598072052},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.4554824233055115},{"id":"https://openalex.org/keywords/sense-amplifier","display_name":"Sense amplifier","score":0.4210795760154724},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.41433846950531006},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.3654863238334656},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.34348732233047485},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.26511523127555847},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.20083534717559814}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.9014298915863037},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6966955661773682},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6031164526939392},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.5912623405456543},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.5239964723587036},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.483051598072052},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.4554824233055115},{"id":"https://openalex.org/C32666082","wikidata":"https://www.wikidata.org/wiki/Q7450979","display_name":"Sense amplifier","level":3,"score":0.4210795760154724},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.41433846950531006},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.3654863238334656},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34348732233047485},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.26511523127555847},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.20083534717559814}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/pact.2015.58","is_oa":false,"landing_page_url":"https://doi.org/10.1109/pact.2015.58","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 International Conference on Parallel Architecture and Compilation (PACT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2041271371","https://openalex.org/W2048231554","https://openalex.org/W2102449048","https://openalex.org/W2134345525","https://openalex.org/W2147657366","https://openalex.org/W6661150524"],"related_works":["https://openalex.org/W2900372418","https://openalex.org/W2268596372","https://openalex.org/W2544687927","https://openalex.org/W2122895920","https://openalex.org/W1977963439","https://openalex.org/W956872486","https://openalex.org/W2999811406","https://openalex.org/W2246887984","https://openalex.org/W3192890818","https://openalex.org/W3091205277"],"abstract_inverted_index":{"DRAM":[0,48],"consumes":[1],"significant":[2],"static":[3,26],"energy":[4,27,39,56],"both":[5,47,54],"in":[6,68],"active":[7],"and":[8,15,28,36,49,57],"idle":[9],"state":[10],"due":[11],"to":[12,89],"continuous":[13],"leakage":[14],"refresh":[16],"power.":[17],"Various":[18],"byte-addressable":[19],"non-volatile":[20],"memory":[21,84],"(NVM)":[22],"technologies":[23],"promise":[24],"near-zero":[25],"persistence,":[29],"however":[30],"they":[31],"suffer":[32],"from":[33],"increased":[34,37],"latency":[35],"dynamic":[38],"than":[40],"DRAM.":[41],"A":[42],"hybrid":[43,81],"main":[44,83],"memory,":[45],"containing":[46],"NVM":[50],"components,":[51],"can":[52],"provide":[53],"low":[55],"high":[58],"performance":[59],"although":[60],"such":[61],"organizations":[62],"require":[63],"that":[64],"data":[65],"is":[66],"placed":[67],"the":[69],"appropriate":[70],"component.":[71],"We":[72],"propose":[73],"a":[74,80],"user-level":[75],"software":[76],"management":[77],"methodology":[78],"for":[79],"DRAM/NVM":[82],"system":[85],"with":[86],"an":[87],"aim":[88],"reduce":[90],"energy.":[91]},"counts_by_year":[{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":5},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}