{"id":"https://openalex.org/W7126108725","doi":"https://doi.org/10.1109/nfv-sdn66355.2025.11349482","title":"Design Principles for Accelerated Programmable Edge Computing in Future 6G Architectures","display_name":"Design Principles for Accelerated Programmable Edge Computing in Future 6G Architectures","publication_year":2025,"publication_date":"2025-11-10","ids":{"openalex":"https://openalex.org/W7126108725","doi":"https://doi.org/10.1109/nfv-sdn66355.2025.11349482"},"language":"en","primary_location":{"id":"doi:10.1109/nfv-sdn66355.2025.11349482","is_oa":false,"landing_page_url":"https://doi.org/10.1109/nfv-sdn66355.2025.11349482","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Conference on Network Function Virtualization and Software-Defined Networking (NFV-SDN)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066330654","display_name":"Filippo Carloni","orcid":"https://orcid.org/0000-0001-7084-7184"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Filippo Carloni","raw_affiliation_strings":["Poltecnico di Milano and CNIT,Milan,Italy"],"affiliations":[{"raw_affiliation_string":"Poltecnico di Milano and CNIT,Milan,Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054266377","display_name":"Angelo Tulumello","orcid":"https://orcid.org/0000-0003-3607-1524"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Angelo Tulumello","raw_affiliation_strings":["Università di Roma Tor Vergata and CNIT,Rome,Italy"],"affiliations":[{"raw_affiliation_string":"Università di Roma Tor Vergata and CNIT,Rome,Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065685327","display_name":"Andrea Castelli","orcid":"https://orcid.org/0000-0003-2544-2887"},"institutions":[{"id":"https://openalex.org/I4210140707","display_name":"Brainstorm (Spain)","ror":"https://ror.org/03z3n0g53","country_code":"ES","type":"company","lineage":["https://openalex.org/I4210140707"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Andrea Castelli","raw_affiliation_strings":["Brainstorm Multimedia S.L.,Valencia,Spain"],"affiliations":[{"raw_affiliation_string":"Brainstorm Multimedia S.L.,Valencia,Spain","institution_ids":["https://openalex.org/I4210140707"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013519573","display_name":"Javier Montesa","orcid":null},"institutions":[{"id":"https://openalex.org/I4210140707","display_name":"Brainstorm (Spain)","ror":"https://ror.org/03z3n0g53","country_code":"ES","type":"company","lineage":["https://openalex.org/I4210140707"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Javier Montesa","raw_affiliation_strings":["Brainstorm Multimedia S.L.,Valencia,Spain"],"affiliations":[{"raw_affiliation_string":"Brainstorm Multimedia S.L.,Valencia,Spain","institution_ids":["https://openalex.org/I4210140707"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Gianni Antichi","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gianni Antichi","raw_affiliation_strings":["Poltecnico di Milano and CNIT,Milan,Italy"],"affiliations":[{"raw_affiliation_string":"Poltecnico di Milano and CNIT,Milan,Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Giuseppe Bianchi","orcid":null},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Giuseppe Bianchi","raw_affiliation_strings":["Università di Roma Tor Vergata and CNIT,Rome,Italy"],"affiliations":[{"raw_affiliation_string":"Università di Roma Tor Vergata and CNIT,Rome,Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080554446","display_name":"Giuseppe Gaetano Letti\u00e9ri","orcid":null},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Giuseppe Lettieri","raw_affiliation_strings":["Università di Pisa and CNIT,Pisa,Italy"],"affiliations":[{"raw_affiliation_string":"Università di Pisa and CNIT,Pisa,Italy","institution_ids":["https://openalex.org/I108290504"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051501620","display_name":"Gregorio Procissi","orcid":"https://orcid.org/0000-0001-5604-6129"},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gregorio Procissi","raw_affiliation_strings":["Università di Pisa and CNIT,Pisa,Italy"],"affiliations":[{"raw_affiliation_string":"Università di Pisa and CNIT,Pisa,Italy","institution_ids":["https://openalex.org/I108290504"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5066330654"],"corresponding_institution_ids":["https://openalex.org/I93860229"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.7149536,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10714","display_name":"Software-Defined Networks and 5G","score":0.7419999837875366,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10714","display_name":"Software-Defined Networks and 5G","score":0.7419999837875366,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10273","display_name":"IoT and Edge/Fog Computing","score":0.18279999494552612,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14347","display_name":"Big Data and Digital Economy","score":0.012000000104308128,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/network-processor","display_name":"Network processor","score":0.6434999704360962},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4853000044822693},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4465000033378601},{"id":"https://openalex.org/keywords/edge-device","display_name":"Edge device","score":0.44029998779296875},{"id":"https://openalex.org/keywords/network-interface","display_name":"Network interface","score":0.4162999987602234},{"id":"https://openalex.org/keywords/enhanced-data-rates-for-gsm-evolution","display_name":"Enhanced Data Rates for GSM Evolution","score":0.41589999198913574},{"id":"https://openalex.org/keywords/networking-hardware","display_name":"Networking hardware","score":0.4072999954223633},{"id":"https://openalex.org/keywords/network-architecture","display_name":"Network architecture","score":0.4016999900341034},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.40149998664855957},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.3961000144481659}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7955999970436096},{"id":"https://openalex.org/C74366991","wikidata":"https://www.wikidata.org/wiki/Q2755335","display_name":"Network processor","level":3,"score":0.6434999704360962},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6399000287055969},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5472000241279602},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4853000044822693},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4465000033378601},{"id":"https://openalex.org/C138236772","wikidata":"https://www.wikidata.org/wiki/Q25098575","display_name":"Edge device","level":3,"score":0.44029998779296875},{"id":"https://openalex.org/C103987645","wikidata":"https://www.wikidata.org/wiki/Q985806","display_name":"Network interface","level":3,"score":0.4162999987602234},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.41589999198913574},{"id":"https://openalex.org/C159631557","wikidata":"https://www.wikidata.org/wiki/Q1546066","display_name":"Networking hardware","level":2,"score":0.4072999954223633},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.40299999713897705},{"id":"https://openalex.org/C193415008","wikidata":"https://www.wikidata.org/wiki/Q639681","display_name":"Network architecture","level":2,"score":0.4016999900341034},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.40149998664855957},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.3961000144481659},{"id":"https://openalex.org/C34165917","wikidata":"https://www.wikidata.org/wiki/Q188267","display_name":"Programming paradigm","level":2,"score":0.3628000020980835},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.3463999927043915},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.34360000491142273},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.33640000224113464},{"id":"https://openalex.org/C147358964","wikidata":"https://www.wikidata.org/wiki/Q1200992","display_name":"Abstraction layer","level":3,"score":0.33059999346733093},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.3206000030040741},{"id":"https://openalex.org/C2778456923","wikidata":"https://www.wikidata.org/wiki/Q5337692","display_name":"Edge computing","level":3,"score":0.3181999921798706},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.314300000667572},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.31349998712539673},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.305400013923645},{"id":"https://openalex.org/C2780378061","wikidata":"https://www.wikidata.org/wiki/Q25351891","display_name":"Service (business)","level":2,"score":0.2924000024795532},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.28769999742507935},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.28679999709129333},{"id":"https://openalex.org/C46637626","wikidata":"https://www.wikidata.org/wiki/Q6693015","display_name":"Low latency (capital markets)","level":2,"score":0.2833999991416931},{"id":"https://openalex.org/C31352089","wikidata":"https://www.wikidata.org/wiki/Q3750474","display_name":"Systems design","level":2,"score":0.27790001034736633},{"id":"https://openalex.org/C76518257","wikidata":"https://www.wikidata.org/wiki/Q271680","display_name":"Software framework","level":5,"score":0.272599995136261},{"id":"https://openalex.org/C114563136","wikidata":"https://www.wikidata.org/wiki/Q19725982","display_name":"Network planning and design","level":2,"score":0.2678999900817871},{"id":"https://openalex.org/C79974875","wikidata":"https://www.wikidata.org/wiki/Q483639","display_name":"Cloud computing","level":2,"score":0.266400009393692},{"id":"https://openalex.org/C98025372","wikidata":"https://www.wikidata.org/wiki/Q477538","display_name":"Systems architecture","level":3,"score":0.2651999890804291},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2619999945163727},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.259799987077713},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.25450000166893005},{"id":"https://openalex.org/C2779618445","wikidata":"https://www.wikidata.org/wiki/Q1640628","display_name":"Network service","level":2,"score":0.2542000114917755}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/nfv-sdn66355.2025.11349482","is_oa":false,"landing_page_url":"https://doi.org/10.1109/nfv-sdn66355.2025.11349482","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Conference on Network Function Virtualization and Software-Defined Networking (NFV-SDN)","raw_type":"proceedings-article"},{"id":"pmh:oai:arpi.unipi.it:11568/1345627","is_oa":false,"landing_page_url":"https://hdl.handle.net/11568/1345627","pdf_url":null,"source":{"id":"https://openalex.org/S4377196265","display_name":"CINECA IRIS Institutial research information system (University of Pisa)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I108290504","host_organization_name":"University of Pisa","host_organization_lineage":["https://openalex.org/I108290504"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:re.public.polimi.it:11311/1311436","is_oa":false,"landing_page_url":"https://hdl.handle.net/11311/1311436","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.648737907409668,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320334322","display_name":"HORIZON EUROPE Framework Programme","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W2487095677","https://openalex.org/W2744693751","https://openalex.org/W2761338514","https://openalex.org/W2769986458","https://openalex.org/W2903038868","https://openalex.org/W2944456270","https://openalex.org/W2968108410","https://openalex.org/W2981096252","https://openalex.org/W3046227456","https://openalex.org/W3046440678","https://openalex.org/W3046697300","https://openalex.org/W3046771328","https://openalex.org/W3091752016","https://openalex.org/W3189425713","https://openalex.org/W3209399855","https://openalex.org/W4286203032","https://openalex.org/W4290991009","https://openalex.org/W4290991465","https://openalex.org/W4327911843","https://openalex.org/W4386365337","https://openalex.org/W4392453365","https://openalex.org/W4401211770","https://openalex.org/W4404955145","https://openalex.org/W4407130344"],"related_works":[],"abstract_inverted_index":{"The":[0,101],"growing":[1],"demand":[2],"for":[3,82],"high":[4,104],"throughput":[5],"and":[6,21,84,147],"ultra-low":[7],"latency":[8],"in":[9],"emerging":[10],"6G":[11],"networks":[12],"requires":[13],"moving":[14],"service":[15],"processing":[16,46,120],"closer":[17],"to":[18,60],"end":[19],"users":[20],"enabling":[22],"powerful":[23],"computational":[24],"offloading":[25,49,86],"within":[26],"the":[27,137,141],"network":[28,54,62,99,131],"infrastructure.":[29],"This":[30,133],"work":[31],"proposes":[32],"Accelerated":[33],"Programmable":[34,92],"Edge":[35],"Computing":[36],"(APEC),":[37],"a":[38,91],"unified,":[39],"flexible":[40],"framework":[41,102],"that":[42],"combines":[43],"high-performance":[44],"CPU":[45],"with":[47,64,72],"hardware":[48,74,83],"capabilities":[50],"provided":[51],"by":[52],"programmable":[53],"interface":[55],"cards":[56],"(NICs).":[57],"APEC":[58,142],"aims":[59],"enhance":[61],"performance":[63,105],"an":[65],"adaptable":[66],"platform":[67],"merging":[68],"high-level":[69],"programming":[70],"expressiveness":[71],"specialized":[73,130],"acceleration.":[75],"Its":[76],"architecture":[77],"exposes":[78],"custom":[79],"primitives":[80],"optimized":[81],"kernel-level":[85,119],"or":[87],"user-space":[88],"acceleration,":[89],"via":[90,106],"Abstraction":[93],"Interface,":[94],"facilitating":[95],"efficient":[96],"execution":[97],"of":[98,140],"functions.":[100],"provides":[103,136],"multiple":[107],"acceleration":[108],"strategies.":[109],"It":[110],"optimizes":[111],"data":[112],"handling":[113],"through":[114],"high-speed":[115],"software":[116],"while":[117],"advanced":[118],"further":[121],"reduces":[122],"latency,":[123],"whereas":[124],"performance-critical":[125],"tasks":[126],"are":[127],"executed":[128],"on":[129],"hardware.":[132],"position":[134],"paper":[135],"core":[138],"components":[139],"framework,":[143],"discussing":[144],"their":[145],"rationale":[146],"integration.":[148]},"counts_by_year":[],"updated_date":"2026-04-09T08:11:56.329763","created_date":"2026-01-30T00:00:00"}