{"id":"https://openalex.org/W2154858895","doi":"https://doi.org/10.1109/mwscas.2014.6908526","title":"A 3.86mW 106.4dB SNDR Delta-Sigma modulator based on Switched-Opamp for audio codec","display_name":"A 3.86mW 106.4dB SNDR Delta-Sigma modulator based on Switched-Opamp for audio codec","publication_year":2014,"publication_date":"2014-08-01","ids":{"openalex":"https://openalex.org/W2154858895","doi":"https://doi.org/10.1109/mwscas.2014.6908526","mag":"2154858895"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2014.6908526","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2014.6908526","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065270536","display_name":"Zhongyi Huang","orcid":"https://orcid.org/0000-0002-5623-4864"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]},{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Zhongyi Huang","raw_affiliation_strings":["Institute of VLSI design, Zhejiang University, Hangzhou, P.R. China"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI design, Zhejiang University, Hangzhou, P.R. China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066353712","display_name":"Menglian Zhao","orcid":"https://orcid.org/0000-0002-2500-2892"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]},{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Menglian Zhao","raw_affiliation_strings":["Institute of VLSI design, Zhejiang University, Hangzhou, P.R. China"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI design, Zhejiang University, Hangzhou, P.R. China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062367470","display_name":"Xiaolin Yang","orcid":"https://orcid.org/0000-0001-9900-528X"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]},{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaolin Yang","raw_affiliation_strings":["Institute of VLSI design, Zhejiang University, Hangzhou, P.R. China"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI design, Zhejiang University, Hangzhou, P.R. China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061386400","display_name":"Liyu Lin","orcid":"https://orcid.org/0000-0001-8663-7448"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Liyu Lin","raw_affiliation_strings":["Institute of VLSI design, Zhejiang University, Hangzhou, P.R. China"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI design, Zhejiang University, Hangzhou, P.R. China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100677577","display_name":"Xiaobo Wu","orcid":"https://orcid.org/0000-0002-1068-5934"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]},{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaobo Wu","raw_affiliation_strings":["Institute of VLSI design, Zhejiang University, Hangzhou, P.R. China"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI design, Zhejiang University, Hangzhou, P.R. China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5065270536"],"corresponding_institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"],"apc_list":null,"apc_paid":null,"fwci":0.1868,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.57645554,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"3","issue":null,"first_page":"761","last_page":"764"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/delta-sigma-modulation","display_name":"Delta-sigma modulation","score":0.7983355522155762},{"id":"https://openalex.org/keywords/operational-amplifier","display_name":"Operational amplifier","score":0.694212794303894},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5989246964454651},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5754249095916748},{"id":"https://openalex.org/keywords/slew-rate","display_name":"Slew rate","score":0.5693303346633911},{"id":"https://openalex.org/keywords/codec","display_name":"Codec","score":0.5190470814704895},{"id":"https://openalex.org/keywords/chopper","display_name":"Chopper","score":0.5091819167137146},{"id":"https://openalex.org/keywords/switched-capacitor","display_name":"Switched capacitor","score":0.4563690721988678},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4267970025539398},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.38286495208740234},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.36106330156326294},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.34916555881500244},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3400026559829712},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.28308045864105225},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.19367733597755432},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13602310419082642}],"concepts":[{"id":"https://openalex.org/C68754193","wikidata":"https://www.wikidata.org/wiki/Q1184820","display_name":"Delta-sigma modulation","level":3,"score":0.7983355522155762},{"id":"https://openalex.org/C145366948","wikidata":"https://www.wikidata.org/wiki/Q178947","display_name":"Operational amplifier","level":4,"score":0.694212794303894},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5989246964454651},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5754249095916748},{"id":"https://openalex.org/C82517063","wikidata":"https://www.wikidata.org/wiki/Q1591315","display_name":"Slew rate","level":3,"score":0.5693303346633911},{"id":"https://openalex.org/C161765866","wikidata":"https://www.wikidata.org/wiki/Q184748","display_name":"Codec","level":2,"score":0.5190470814704895},{"id":"https://openalex.org/C2780191706","wikidata":"https://www.wikidata.org/wiki/Q191658","display_name":"Chopper","level":3,"score":0.5091819167137146},{"id":"https://openalex.org/C103357873","wikidata":"https://www.wikidata.org/wiki/Q572656","display_name":"Switched capacitor","level":4,"score":0.4563690721988678},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4267970025539398},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.38286495208740234},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.36106330156326294},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.34916555881500244},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3400026559829712},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.28308045864105225},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.19367733597755432},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13602310419082642}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2014.6908526","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2014.6908526","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320335787","display_name":"Fundamental Research Funds for the Central Universities","ror":null},{"id":"https://openalex.org/F4320338464","display_name":"Natural Science Foundation of Zhejiang Province","ror":"https://ror.org/01h0zpd94"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1444521707","https://openalex.org/W1519910072","https://openalex.org/W1600322442","https://openalex.org/W2049573496","https://openalex.org/W2079351711","https://openalex.org/W2103805676","https://openalex.org/W2114753685","https://openalex.org/W2154143688","https://openalex.org/W2689743116","https://openalex.org/W6631066600","https://openalex.org/W6682815149"],"related_works":["https://openalex.org/W2376014514","https://openalex.org/W2391645806","https://openalex.org/W2102712905","https://openalex.org/W1491867692","https://openalex.org/W2044524120","https://openalex.org/W2493585380","https://openalex.org/W2999366224","https://openalex.org/W1977097430","https://openalex.org/W2982347447","https://openalex.org/W3201593851"],"abstract_inverted_index":{"A":[0,29],"low-power":[1],"high-resolution":[2],"Delta-Sigma":[3],"modulator":[4,19,86],"for":[5,119],"audio":[6,120],"codec,":[7],"designed":[8],"in":[9,81],"Global-Foundries":[10],"BCD":[11],"0.18\u03bcm":[12],"1P4M":[13],"CMOS":[14],"process,":[15],"is":[16,41,117],"presented.":[17],"The":[18,54,84],"employs":[20],"a":[21,27,98,104,110],"fourth-order":[22],"single-loop":[23],"feedforward":[24],"topology":[25],"with":[26,97],"3bit-quantizer.":[28],"novel":[30],"structure":[31],"of":[32,47,101,107,114],"Switched-Opamp":[33],"(SO)":[34],"utilizing":[35],"current-starvation":[36],"and":[37,50,57,74,91,109],"Slew-Rate":[38],"(SR)":[39],"boosting":[40],"adopted":[42],"to":[43,62,68],"meet":[44],"the":[45,70],"requirements":[46],"high":[48,111],"performance":[49],"fast":[51],"settling":[52],"time.":[53],"opamp-shared":[55],"technique":[56],"two-step":[58],"summation":[59],"are":[60,79],"used":[61],"reduce":[63],"power":[64,89],"dissipation":[65],"further.":[66],"Meanwhile,":[67],"improve":[69],"resolution,":[71],"chopper-stabilization":[72],"(CHS)":[73],"pseudo":[75],"data-weighted-averaging":[76],"(PDWA)":[77],"circuits":[78],"employed":[80],"this":[82],"paper.":[83],"proposed":[85],"achieves":[87],"3.86mW":[88],"consumption":[90],"106.4dB":[92],"Signal-to-Noise":[93],"Distortion":[94],"Ratio":[95],"(SNDR)":[96],"FOM":[99],"value":[100],"0.56pJ/conv.-step":[102],"at":[103],"supply":[105],"voltage":[106],"3.3V":[108],"working":[112],"frequency":[113],"6.25MHz,":[115],"which":[116],"suitable":[118],"applications.":[121]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
