{"id":"https://openalex.org/W2128021694","doi":"https://doi.org/10.1109/mse.2005.19","title":"An FPGA-Based Daughtercard for TI\u2019s C6000 family of DSKs","display_name":"An FPGA-Based Daughtercard for TI\u2019s C6000 family of DSKs","publication_year":2006,"publication_date":"2006-10-11","ids":{"openalex":"https://openalex.org/W2128021694","doi":"https://doi.org/10.1109/mse.2005.19","mag":"2128021694"},"language":"en","primary_location":{"id":"doi:10.1109/mse.2005.19","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mse.2005.19","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Conference on Microelectronic Systems Education (MSE'05)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037634362","display_name":"Manik Gadhiok","orcid":null},"institutions":[{"id":"https://openalex.org/I74775410","display_name":"Rice University","ror":"https://ror.org/008zs3103","country_code":"US","type":"education","lineage":["https://openalex.org/I74775410"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Gadhiok","raw_affiliation_strings":["Department of Electrical & Computer Engineering, Rice University, Houston, TX, USA","Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical & Computer Engineering, Rice University, Houston, TX, USA","institution_ids":["https://openalex.org/I74775410"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA","institution_ids":["https://openalex.org/I74775410"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054103715","display_name":"Rebecca Hardy","orcid":"https://orcid.org/0000-0001-9949-0799"},"institutions":[{"id":"https://openalex.org/I74775410","display_name":"Rice University","ror":"https://ror.org/008zs3103","country_code":"US","type":"education","lineage":["https://openalex.org/I74775410"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Hardy","raw_affiliation_strings":["Department of Electrical & Computer Engineering, Rice University, Houston, TX, USA","Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical & Computer Engineering, Rice University, Houston, TX, USA","institution_ids":["https://openalex.org/I74775410"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA","institution_ids":["https://openalex.org/I74775410"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090417167","display_name":"Patrick Murphy","orcid":null},"institutions":[{"id":"https://openalex.org/I74775410","display_name":"Rice University","ror":"https://ror.org/008zs3103","country_code":"US","type":"education","lineage":["https://openalex.org/I74775410"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"P. Murphy","raw_affiliation_strings":["Department of Electrical & Computer Engineering, Rice University, Houston, TX, USA","Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical & Computer Engineering, Rice University, Houston, TX, USA","institution_ids":["https://openalex.org/I74775410"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA","institution_ids":["https://openalex.org/I74775410"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041147182","display_name":"J.P. Frantz","orcid":null},"institutions":[{"id":"https://openalex.org/I74775410","display_name":"Rice University","ror":"https://ror.org/008zs3103","country_code":"US","type":"education","lineage":["https://openalex.org/I74775410"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.P. Frantz","raw_affiliation_strings":["Department of Electrical & Computer Engineering, Rice University, Houston, TX, USA","Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical & Computer Engineering, Rice University, Houston, TX, USA","institution_ids":["https://openalex.org/I74775410"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA","institution_ids":["https://openalex.org/I74775410"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103357257","display_name":"Hyeokho Choi","orcid":null},"institutions":[{"id":"https://openalex.org/I74775410","display_name":"Rice University","ror":"https://ror.org/008zs3103","country_code":"US","type":"education","lineage":["https://openalex.org/I74775410"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hyeokho Choi","raw_affiliation_strings":["Department of Electrical & Computer Engineering, Rice University, Houston, TX, USA","Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical & Computer Engineering, Rice University, Houston, TX, USA","institution_ids":["https://openalex.org/I74775410"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA","institution_ids":["https://openalex.org/I74775410"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5085983829","display_name":"Joseph R. Cavallaro","orcid":"https://orcid.org/0000-0002-9841-1806"},"institutions":[{"id":"https://openalex.org/I74775410","display_name":"Rice University","ror":"https://ror.org/008zs3103","country_code":"US","type":"education","lineage":["https://openalex.org/I74775410"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.R. Cavallaro","raw_affiliation_strings":["Department of Electrical & Computer Engineering, Rice University, Houston, TX, USA","Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical & Computer Engineering, Rice University, Houston, TX, USA","institution_ids":["https://openalex.org/I74775410"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA","institution_ids":["https://openalex.org/I74775410"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I74775410"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.28786982,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"85","last_page":"86"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11283","display_name":"Experimental Learning in Engineering","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2214","display_name":"Media Technology"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11283","display_name":"Experimental Learning in Engineering","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2214","display_name":"Media Technology"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9894999861717224,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9872000217437744,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8540740013122559},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7391991019248962},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7372065782546997},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.5966070890426636},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5950725674629211},{"id":"https://openalex.org/keywords/leverage","display_name":"Leverage (statistics)","score":0.5856124758720398},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.5549333691596985},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5075806379318237},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4800606667995453},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.4670637547969818},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.42075881361961365},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.31792840361595154}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8540740013122559},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7391991019248962},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7372065782546997},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.5966070890426636},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5950725674629211},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.5856124758720398},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.5549333691596985},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5075806379318237},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4800606667995453},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4670637547969818},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.42075881361961365},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.31792840361595154},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/mse.2005.19","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mse.2005.19","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Conference on Microelectronic Systems Education (MSE'05)","raw_type":"proceedings-article"},{"id":"pmh:oai:repository.rice.edu:1911/19892","is_oa":false,"landing_page_url":"https://hdl.handle.net/1911/19892","pdf_url":null,"source":{"id":"https://openalex.org/S4306401268","display_name":"Rice Digital Scholarship Archive (Rice University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I74775410","host_organization_name":"Rice University","host_organization_lineage":["https://openalex.org/I74775410"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference paper"},{"id":"pmh:oai:scholarship.rice.edu:1911/19892","is_oa":false,"landing_page_url":"http://hdl.handle.net/1911/19892","pdf_url":null,"source":{"id":"https://openalex.org/S4306401268","display_name":"Rice Digital Scholarship Archive (Rice University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I74775410","host_organization_name":"Rice University","host_organization_lineage":["https://openalex.org/I74775410"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Conference paper"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G1934746744","display_name":"CISE Research Resources:    A Comprehensive Multi-Tier Wireless Network Development Platform","funder_award_id":"0224458","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G5013177805","display_name":"MRI: Development of a National University Wireless Testbed: Rice Configurable Baseband Architecture","funder_award_id":"0321266","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2101262125","https://openalex.org/W2157370237","https://openalex.org/W6675087838"],"related_works":["https://openalex.org/W1876592433","https://openalex.org/W2998132311","https://openalex.org/W2083269738","https://openalex.org/W2207067480","https://openalex.org/W4383823603","https://openalex.org/W1692883217","https://openalex.org/W2406926880","https://openalex.org/W2332075903","https://openalex.org/W1579891439","https://openalex.org/W2291257309"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3,66],"present":[4],"an":[5],"FPGA-based":[6],"daughtercard":[7,73],"designed":[8,20],"for":[9,21,28,42,62],"TIs":[10],"C6000family":[11],"of":[12,45],"DSP":[13],"starter":[14],"kits":[15],"(DSKs).":[16],"The":[17,72],"hardware,":[18],"initially":[19],"a":[22,26,79,87],"course":[23],"project,":[24],"provides":[25],"platform":[27],"studying":[29],"heterogeneous":[30],"systems":[31],"and":[32,49,53,78,94],"hardware":[33,74],"software":[34,80],"co-design.":[35],"Students":[36],"can":[37],"leverage":[38],"the":[39,92],"DSK-FPGA":[40],"system":[41,54,63],"rapid":[43],"prototyping":[44],"signal":[46],"processing":[47],"algorithms":[48],"to":[50,68,85],"study":[51],"task-partitioning":[52],"integration.":[55],"These":[56],"techniques":[57],"are":[58],"becoming":[59],"increasingly":[60],"important":[61],"designers":[64],"as":[65],"move":[67],"system-on-chip":[69],"(SoC)":[70],"devices.":[71],"is":[75,82],"fully":[76],"functional,":[77],"package":[81],"being":[83],"developed":[84],"provide":[86],"seamless":[88],"communication":[89],"interface":[90],"between":[91],"DSK":[93],"FPGA.":[95]},"counts_by_year":[],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2016-06-24T00:00:00"}
