{"id":"https://openalex.org/W4240683705","doi":"https://doi.org/10.1109/micro.1996.566467","title":"Software pipelining loops with conditional branches","display_name":"Software pipelining loops with conditional branches","publication_year":2002,"publication_date":"2002-12-24","ids":{"openalex":"https://openalex.org/W4240683705","doi":"https://doi.org/10.1109/micro.1996.566467"},"language":"en","primary_location":{"id":"doi:10.1109/micro.1996.566467","is_oa":false,"landing_page_url":"https://doi.org/10.1109/micro.1996.566467","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029046696","display_name":"M.G. Stoodley","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"M.G. Stoodley","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025419480","display_name":"C.G. Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"C.G. Lee","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5029046696"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":1.6522,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.85314967,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"262","last_page":"273"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/software-pipelining","display_name":"Software pipelining","score":0.9866005182266235},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8897445797920227},{"id":"https://openalex.org/keywords/very-long-instruction-word","display_name":"Very long instruction word","score":0.8524478673934937},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7666683197021484},{"id":"https://openalex.org/keywords/instruction-scheduling","display_name":"Instruction scheduling","score":0.5026874542236328},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.48480740189552307},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.46701839566230774},{"id":"https://openalex.org/keywords/instruction-level-parallelism","display_name":"Instruction-level parallelism","score":0.46375516057014465},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.4420822560787201},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.4140850901603699},{"id":"https://openalex.org/keywords/loop-optimization","display_name":"Loop optimization","score":0.4130253195762634},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.3520470857620239},{"id":"https://openalex.org/keywords/optimizing-compiler","display_name":"Optimizing compiler","score":0.24562638998031616},{"id":"https://openalex.org/keywords/dynamic-priority-scheduling","display_name":"Dynamic priority scheduling","score":0.18441137671470642},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.16634079813957214},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.11577001214027405},{"id":"https://openalex.org/keywords/two-level-scheduling","display_name":"Two-level scheduling","score":0.11461952328681946}],"concepts":[{"id":"https://openalex.org/C188854837","wikidata":"https://www.wikidata.org/wiki/Q268469","display_name":"Software pipelining","level":3,"score":0.9866005182266235},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8897445797920227},{"id":"https://openalex.org/C170595534","wikidata":"https://www.wikidata.org/wiki/Q249743","display_name":"Very long instruction word","level":2,"score":0.8524478673934937},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7666683197021484},{"id":"https://openalex.org/C73564150","wikidata":"https://www.wikidata.org/wiki/Q11417093","display_name":"Instruction scheduling","level":5,"score":0.5026874542236328},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.48480740189552307},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.46701839566230774},{"id":"https://openalex.org/C140763907","wikidata":"https://www.wikidata.org/wiki/Q2714055","display_name":"Instruction-level parallelism","level":3,"score":0.46375516057014465},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.4420822560787201},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.4140850901603699},{"id":"https://openalex.org/C29331672","wikidata":"https://www.wikidata.org/wiki/Q3354468","display_name":"Loop optimization","level":4,"score":0.4130253195762634},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.3520470857620239},{"id":"https://openalex.org/C190902152","wikidata":"https://www.wikidata.org/wiki/Q1325106","display_name":"Optimizing compiler","level":3,"score":0.24562638998031616},{"id":"https://openalex.org/C107568181","wikidata":"https://www.wikidata.org/wiki/Q5319000","display_name":"Dynamic priority scheduling","level":3,"score":0.18441137671470642},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.16634079813957214},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.11577001214027405},{"id":"https://openalex.org/C119948110","wikidata":"https://www.wikidata.org/wiki/Q7858726","display_name":"Two-level scheduling","level":4,"score":0.11461952328681946},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/micro.1996.566467","is_oa":false,"landing_page_url":"https://doi.org/10.1109/micro.1996.566467","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W90084074","https://openalex.org/W1534890693","https://openalex.org/W1963718362","https://openalex.org/W1990529315","https://openalex.org/W2012512596","https://openalex.org/W2024176773","https://openalex.org/W2054652902","https://openalex.org/W2063639637","https://openalex.org/W2075137135","https://openalex.org/W2122439715","https://openalex.org/W2123412205","https://openalex.org/W2123914963","https://openalex.org/W2129962996","https://openalex.org/W2140311411","https://openalex.org/W2170803003","https://openalex.org/W2296760900","https://openalex.org/W2576288252","https://openalex.org/W3139787704","https://openalex.org/W3163711330","https://openalex.org/W4229748763","https://openalex.org/W4232919122","https://openalex.org/W4238759521","https://openalex.org/W4239600267","https://openalex.org/W4247930130","https://openalex.org/W4252494437","https://openalex.org/W4301667331","https://openalex.org/W6684486700"],"related_works":["https://openalex.org/W2993981457","https://openalex.org/W25845550","https://openalex.org/W1991837811","https://openalex.org/W2025289275","https://openalex.org/W128821325","https://openalex.org/W3143608323","https://openalex.org/W1978984686","https://openalex.org/W2161926026","https://openalex.org/W1506090700","https://openalex.org/W1582417364"],"abstract_inverted_index":{"Software":[0],"pipelining":[1,22,111,161,164],"is":[2,14,54,77,147],"an":[3,38],"aggressive":[4],"scheduling":[5,100],"technique":[6],"that":[7,31,46,83],"generates":[8],"efficient":[9,69],"code":[10,70,132],"for":[11,17,62,71,109],"loops":[12,30,165],"and":[13,101,123],"particularly":[15],"effective":[16],"VLIW":[18,135],"architectures.":[19],"Few":[20],"software":[21,51,110,160],"algorithms,":[23,104],"however,":[24],"are":[25],"able":[26,148],"to":[27,56,149,153],"efficiently":[28],"schedule":[29],"contain":[32],"conditional":[33,167],"branches.":[34,168],"We":[35,113],"have":[36,114,124],"developed":[37],"algorithm":[39,118],"we":[40],"call":[41],"All":[42],"Paths":[43],"Pipelining":[44],"(APP)":[45],"addresses":[47],"this":[48,94],"shortcoming":[49],"of":[50,65,80],"pipelining.":[52],"APP":[53,92,117,146],"designed":[55],"achieve":[57],"optimal":[58],"or":[59],"near-optimal":[60],"performance":[61,127,157],"any":[63],"run":[64,76],"iterations":[66,82],"while":[67],"providing":[68],"transitioning":[72],"between":[73],"runs.":[74],"A":[75],"the":[78,86,105,116],"execution":[79],"consecutive":[81],"all":[84],"execute":[85],"same":[87],"path":[88],"through":[89],"a":[90,134,139],"loop.":[91],"accomplishes":[93],"by":[95,128,162],"using":[96],"techniques":[97],"from":[98],"modulo":[99],"kernel":[102],"recognition":[103],"two":[106],"main":[107],"approaches":[108],"loops.":[112],"implemented":[115],"in":[119,156],"our":[120],"research":[121],"compiler":[122],"evaluated":[125],"its":[126,130],"executing":[129],"generated":[131],"on":[133],"instruction-set":[136],"simulator.":[137],"For":[138],"processor":[140],"with":[141,166],"five":[142],"heterogeneous":[143],"functional":[144],"units,":[145],"add":[150],"another":[151],"1%":[152],"23%":[154],"increase":[155],"over":[158],"basic":[159],"effectively":[163]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}