{"id":"https://openalex.org/W7133341395","doi":"https://doi.org/10.1109/mdat.2026.3670063","title":"ASIC Tape-Out of the First Side-Channel-Protected Neural Network Design","display_name":"ASIC Tape-Out of the First Side-Channel-Protected Neural Network Design","publication_year":2026,"publication_date":"2026-03-03","ids":{"openalex":"https://openalex.org/W7133341395","doi":"https://doi.org/10.1109/mdat.2026.3670063"},"language":null,"primary_location":{"id":"doi:10.1109/mdat.2026.3670063","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdat.2026.3670063","pdf_url":null,"source":{"id":"https://openalex.org/S4210176427","display_name":"IEEE Design and Test","issn_l":"2168-2356","issn":["2168-2356","2168-2364"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design & Test","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5127951740","display_name":"Anuj Dubey","orcid":null},"institutions":[{"id":"https://openalex.org/I137902535","display_name":"North Carolina State University","ror":"https://ror.org/04tj63d06","country_code":"US","type":"education","lineage":["https://openalex.org/I137902535"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anuj Dubey","raw_affiliation_strings":["Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, USA"],"raw_orcid":"https://orcid.org/0000-0002-5111-3609","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, USA","institution_ids":["https://openalex.org/I137902535"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5123375828","display_name":"Aydin Aysu","orcid":null},"institutions":[{"id":"https://openalex.org/I137902535","display_name":"North Carolina State University","ror":"https://ror.org/04tj63d06","country_code":"US","type":"education","lineage":["https://openalex.org/I137902535"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Aydin Aysu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, USA"],"raw_orcid":"https://orcid.org/0000-0002-5530-8710","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, USA","institution_ids":["https://openalex.org/I137902535"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5085883266","display_name":"Rosario Cammarota","orcid":"https://orcid.org/0000-0002-2965-8987"},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rosario Cammarota","raw_affiliation_strings":["Department of Information and Computer Science, University of California, Irvine, Irvine, CA, USA"],"raw_orcid":"https://orcid.org/0000-0002-2965-8987","affiliations":[{"raw_affiliation_string":"Department of Information and Computer Science, University of California, Irvine, Irvine, CA, USA","institution_ids":["https://openalex.org/I204250578"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.22030061,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"43","issue":"3","first_page":"14","last_page":"22"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12131","display_name":"Wireless Signal Modulation Classification","score":0.2946000099182129,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12131","display_name":"Wireless Signal Modulation Classification","score":0.2946000099182129,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10320","display_name":"Neural Networks and Applications","score":0.11649999767541885,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11689","display_name":"Adversarial Robustness in Machine Learning","score":0.05820000171661377,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.7677000164985657},{"id":"https://openalex.org/keywords/blueprint","display_name":"Blueprint","score":0.6410999894142151},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5343000292778015},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.4449999928474426},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.42289999127388},{"id":"https://openalex.org/keywords/troubleshooting","display_name":"Troubleshooting","score":0.359499990940094},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.3294999897480011},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.3165999948978424},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.29989999532699585}],"concepts":[{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.7677000164985657},{"id":"https://openalex.org/C155911762","wikidata":"https://www.wikidata.org/wiki/Q422321","display_name":"Blueprint","level":2,"score":0.6410999894142151},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6345000267028809},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.567300021648407},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5343000292778015},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4449999928474426},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.42289999127388},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.4041000008583069},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37700000405311584},{"id":"https://openalex.org/C147494362","wikidata":"https://www.wikidata.org/wiki/Q2078905","display_name":"Troubleshooting","level":2,"score":0.359499990940094},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.3294999897480011},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.3165999948978424},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.29989999532699585},{"id":"https://openalex.org/C46686674","wikidata":"https://www.wikidata.org/wiki/Q466303","display_name":"Boosting (machine learning)","level":2,"score":0.2964000105857849},{"id":"https://openalex.org/C31352089","wikidata":"https://www.wikidata.org/wiki/Q3750474","display_name":"Systems design","level":2,"score":0.29510000348091125},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.2939999997615814},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.28940001130104065},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.2881999909877777},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.2838999927043915},{"id":"https://openalex.org/C9652623","wikidata":"https://www.wikidata.org/wiki/Q190109","display_name":"Field (mathematics)","level":2,"score":0.2800999879837036},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.2775000035762787},{"id":"https://openalex.org/C95623464","wikidata":"https://www.wikidata.org/wiki/Q1096149","display_name":"Classifier (UML)","level":2,"score":0.2736999988555908},{"id":"https://openalex.org/C2985179714","wikidata":"https://www.wikidata.org/wiki/Q627335","display_name":"Work flow","level":2,"score":0.2662999927997589},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.25760000944137573},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.2563000023365021},{"id":"https://openalex.org/C159631557","wikidata":"https://www.wikidata.org/wiki/Q1546066","display_name":"Networking hardware","level":2,"score":0.25600001215934753},{"id":"https://openalex.org/C10144332","wikidata":"https://www.wikidata.org/wiki/Q14645","display_name":"Rootkit","level":3,"score":0.25440001487731934},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.25119999051094055}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mdat.2026.3670063","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdat.2026.3670063","pdf_url":null,"source":{"id":"https://openalex.org/S4210176427","display_name":"IEEE Design and Test","issn_l":"2168-2356","issn":["2168-2356","2168-2364"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design & Test","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G2833268871","display_name":null,"funder_award_id":"GRC Task 2908.00","funder_id":"https://openalex.org/F4320306087","funder_display_name":"Semiconductor Research Corporation"}],"funders":[{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2219812381","https://openalex.org/W2751043011","https://openalex.org/W2896947236","https://openalex.org/W3110986688","https://openalex.org/W3118164462","https://openalex.org/W3197298723","https://openalex.org/W3209687107","https://openalex.org/W3216958329","https://openalex.org/W4221015304","https://openalex.org/W4240560709","https://openalex.org/W4281610795","https://openalex.org/W4378174275"],"related_works":[],"abstract_inverted_index":{"This":[0],"work":[1],"presents":[2],"the":[3,7,40,43,65,69,77,112],"tape":[4],"out":[5],"of":[6,114],"first-ever":[8],"side-channel":[9],"protected":[10],"machine":[11],"learning":[12],"(ML)":[13],"classifier":[14],"as":[15],"an":[16],"ASIC.":[17],"Side-channel":[18],"protection":[19],"leverages":[20],"hardware":[21],"masking,":[22],"algorithmic":[23],"shuffling,":[24],"and":[25,31,48,58,64,100,110],"other":[26],"countermeasures":[27],"to":[28,75,97],"mitigated":[29],"power":[30],"electromagnetic":[32],"leakage":[33],"vulnerabilities":[34],"in":[35],"ML":[36,116],"models.":[37],"We":[38,54],"fabricated":[39],"ASIC":[41],"using":[42],"SkyWater":[44],"130nm":[45],"technology":[46],"node":[47],"a":[49,104],"fully":[50],"open-source":[51,78,91],"design":[52,57,80],"flow.":[53],"document":[55],"our":[56],"implementation":[59],"process,":[60],"detailing":[61],"key":[62],"decisions":[63],"challenges":[66],"encountered":[67],"along":[68],"way,":[70],"including":[71],"but":[72],"not":[73],"limited":[74],"integrating":[76],"physical":[79],"flow":[81],"with":[82],"Efabless\u2019":[83],"ChipIgnite":[84],"shuttle":[85],"program.":[86],"Our":[87],"results":[88],"indicate":[89],"that":[90],"tools":[92],"can":[93],"be":[94],"effectively":[95],"used":[96],"produce":[98],"secure":[99,115],"high-performance":[101],"hardware,":[102],"providing":[103],"valuable":[105],"blueprint":[106],"for":[107],"future":[108],"designs":[109],"advancing":[111],"field":[113],"hardware.":[117]},"counts_by_year":[],"updated_date":"2026-08-12T21:12:35.861297","created_date":"2026-03-04T00:00:00"}