{"id":"https://openalex.org/W1585838752","doi":"https://doi.org/10.1109/latw.2015.7102510","title":"Test compression for circuits with multiple scan chains","display_name":"Test compression for circuits with multiple scan chains","publication_year":2015,"publication_date":"2015-03-01","ids":{"openalex":"https://openalex.org/W1585838752","doi":"https://doi.org/10.1109/latw.2015.7102510","mag":"1585838752"},"language":"en","primary_location":{"id":"doi:10.1109/latw.2015.7102510","is_oa":false,"landing_page_url":"https://doi.org/10.1109/latw.2015.7102510","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 16th Latin-American Test Symposium (LATS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101706960","display_name":"Ond\u0159ej Nov\u00e1k","orcid":"https://orcid.org/0000-0002-3030-0616"},"institutions":[{"id":"https://openalex.org/I147009085","display_name":"Technical University of Liberec","ror":"https://ror.org/02jtk7k02","country_code":"CZ","type":"education","lineage":["https://openalex.org/I147009085"]}],"countries":["CZ"],"is_corresponding":true,"raw_author_name":"Ondrej Novak","raw_affiliation_strings":["Institute of Information Technologies and Electronics, Technical University in Liberec, Liberec, Czech Republic"],"affiliations":[{"raw_affiliation_string":"Institute of Information Technologies and Electronics, Technical University in Liberec, Liberec, Czech Republic","institution_ids":["https://openalex.org/I147009085"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047871386","display_name":"Ji\u0159\u00ed Jen\u00ed\u010dek","orcid":"https://orcid.org/0000-0001-6556-8180"},"institutions":[{"id":"https://openalex.org/I147009085","display_name":"Technical University of Liberec","ror":"https://ror.org/02jtk7k02","country_code":"CZ","type":"education","lineage":["https://openalex.org/I147009085"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Jiri Jen\u00edcek","raw_affiliation_strings":["Technical University in Liberec, Liberec, Czech Republic"],"affiliations":[{"raw_affiliation_string":"Technical University in Liberec, Liberec, Czech Republic","institution_ids":["https://openalex.org/I147009085"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066149539","display_name":"Martin Rozkovec","orcid":"https://orcid.org/0000-0001-5221-616X"},"institutions":[{"id":"https://openalex.org/I147009085","display_name":"Technical University of Liberec","ror":"https://ror.org/02jtk7k02","country_code":"CZ","type":"education","lineage":["https://openalex.org/I147009085"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Martin Rozkovec","raw_affiliation_strings":["Institute of Information Technologies and Electronics, Technical University in Liberec, Liberec, Czech Republic"],"affiliations":[{"raw_affiliation_string":"Institute of Information Technologies and Electronics, Technical University in Liberec, Liberec, Czech Republic","institution_ids":["https://openalex.org/I147009085"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5101706960"],"corresponding_institution_ids":["https://openalex.org/I147009085"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.0318104,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9865999817848206,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.8474087715148926},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6722213625907898},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6273967027664185},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.5835887789726257},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5677908062934875},{"id":"https://openalex.org/keywords/linear-feedback-shift-register","display_name":"Linear feedback shift register","score":0.5449224710464478},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5442190766334534},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5267785787582397},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4028641879558563},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.40147238969802856},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3433275520801544},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2476082742214203},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22425249218940735},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08376845717430115}],"concepts":[{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.8474087715148926},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6722213625907898},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6273967027664185},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.5835887789726257},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5677908062934875},{"id":"https://openalex.org/C159862308","wikidata":"https://www.wikidata.org/wiki/Q681101","display_name":"Linear feedback shift register","level":4,"score":0.5449224710464478},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5442190766334534},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5267785787582397},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4028641879558563},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.40147238969802856},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3433275520801544},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2476082742214203},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22425249218940735},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08376845717430115},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/latw.2015.7102510","is_oa":false,"landing_page_url":"https://doi.org/10.1109/latw.2015.7102510","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 16th Latin-American Test Symposium (LATS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4099999964237213}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1589740774","https://openalex.org/W1998663784","https://openalex.org/W2021917057","https://openalex.org/W2094702919","https://openalex.org/W2096852695","https://openalex.org/W2099226121","https://openalex.org/W2101900253","https://openalex.org/W2105282021","https://openalex.org/W2115658300","https://openalex.org/W2118236186","https://openalex.org/W2118919916","https://openalex.org/W2122627795","https://openalex.org/W2122983144","https://openalex.org/W2130149750","https://openalex.org/W2130722990","https://openalex.org/W2135627440","https://openalex.org/W2145675266","https://openalex.org/W2148598008","https://openalex.org/W2155298431","https://openalex.org/W2475928831","https://openalex.org/W3148276846","https://openalex.org/W6635160734","https://openalex.org/W6677894736"],"related_works":["https://openalex.org/W1991602179","https://openalex.org/W2623444083","https://openalex.org/W75082849","https://openalex.org/W3157572643","https://openalex.org/W2154421641","https://openalex.org/W2119351822","https://openalex.org/W2107463329","https://openalex.org/W2340052325","https://openalex.org/W2327770063","https://openalex.org/W3031189840"],"abstract_inverted_index":{"The":[0,28,73],"paper":[1,74],"presents":[2],"a":[3,11,43,52,60,110,114,123,128],"test":[4,20,162,171],"pattern":[5,163],"compression":[6],"method":[7,30],"for":[8,78],"circuits":[9,156],"with":[10,103,113,183],"high":[12],"number":[13,54,130],"of":[14,55,63,87,108,131,186],"parallel":[15,88],"scan":[16,69,82,139],"chains.":[17],"It":[18,58,117],"reduces":[19],"time":[21],"while":[22,173],"it":[23,46,95,126],"keeps":[24],"hardware":[25,97,175],"overhead":[26,176],"low.":[27],"decompression":[29,76,164],"is":[31,39,96,177],"based":[32],"on":[33,148,154],"the":[34,64,68,104,149,160,174,180,184],"continuous":[35],"LFSR":[36,48,65,80,89,102,111,150],"reseeding":[37],"that":[38,45,94,125,159],"used":[40],"in":[41,121],"such":[42,122],"way":[44,124],"enables":[47],"lockout":[49],"escaping":[50],"within":[51],"small":[53],"clock":[56,71],"cycles.":[57],"requires":[59],"separate":[61],"controlling":[62],"decompressor":[66],"and":[67,85,141,169],"chain":[70,83],"inputs.":[72,90],"discusses":[75],"effectiveness":[77],"different":[79],"shapes,":[81],"lengths":[84,172],"numbers":[86],"We":[91],"have":[92,157],"found":[93],"saving":[98],"to":[99],"use":[100],"an":[101,145],"state":[105],"skipping":[106],"instead":[107],"using":[109],"accompanied":[112],"phase":[115],"shifter.":[116],"can":[118],"be":[119],"designed":[120,182],"uses":[127],"lower":[129],"internal":[132],"XOR":[133],"gates,":[134],"guarantees":[135],"maximum":[136],"separation":[137],"between":[138],"chains":[140],"does":[142],"not":[143],"introduce":[144],"extra":[146],"delay":[147],"outputs.":[151],"Experimental":[152],"results":[153],"benchmark":[155],"shown":[158],"presented":[161],"provides":[165],"unreduced":[166],"fault":[167],"coverage":[168],"short":[170],"low":[178],"comparing":[179],"designs":[181],"help":[185],"nowadays":[187],"industrial":[188],"tools.":[189]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}