{"id":"https://openalex.org/W4415822077","doi":"https://doi.org/10.1109/itc58126.2025.00053","title":"Scan Strategies for High Quality Latch Array Testing","display_name":"Scan Strategies for High Quality Latch Array Testing","publication_year":2025,"publication_date":"2025-09-20","ids":{"openalex":"https://openalex.org/W4415822077","doi":"https://doi.org/10.1109/itc58126.2025.00053"},"language":null,"primary_location":{"id":"doi:10.1109/itc58126.2025.00053","is_oa":false,"landing_page_url":"https://doi.org/10.1109/itc58126.2025.00053","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Test Conference (ITC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5091473895","display_name":"Bin Du","orcid":"https://orcid.org/0000-0003-2146-5854"},"institutions":[{"id":"https://openalex.org/I1311921367","display_name":"Advanced Micro Devices (Canada)","ror":"https://ror.org/02yh0k313","country_code":"CA","type":"company","lineage":["https://openalex.org/I1311921367","https://openalex.org/I4210137977"]},{"id":"https://openalex.org/I4210097591","display_name":"Fluidigm (Canada)","ror":"https://ror.org/00xvbmj91","country_code":"CA","type":"company","lineage":["https://openalex.org/I4210097591","https://openalex.org/I922094183"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Bin Du","raw_affiliation_strings":["AMD,CDFX,Markham,Canada"],"affiliations":[{"raw_affiliation_string":"AMD,CDFX,Markham,Canada","institution_ids":["https://openalex.org/I4210097591","https://openalex.org/I1311921367"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108221914","display_name":"Nehal Patel","orcid":null},"institutions":[{"id":"https://openalex.org/I16269868","display_name":"Santa Clara University","ror":"https://ror.org/03ypqe447","country_code":"US","type":"education","lineage":["https://openalex.org/I16269868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nehal Patel","raw_affiliation_strings":["AMD,CDFX,Santa Clara,USA"],"affiliations":[{"raw_affiliation_string":"AMD,CDFX,Santa Clara,USA","institution_ids":["https://openalex.org/I16269868"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Yerong Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I1311921367","display_name":"Advanced Micro Devices (Canada)","ror":"https://ror.org/02yh0k313","country_code":"CA","type":"company","lineage":["https://openalex.org/I1311921367","https://openalex.org/I4210137977"]},{"id":"https://openalex.org/I4210097591","display_name":"Fluidigm (Canada)","ror":"https://ror.org/00xvbmj91","country_code":"CA","type":"company","lineage":["https://openalex.org/I4210097591","https://openalex.org/I922094183"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Yerong Chen","raw_affiliation_strings":["AMD,CDFX,Markham,Canada"],"affiliations":[{"raw_affiliation_string":"AMD,CDFX,Markham,Canada","institution_ids":["https://openalex.org/I4210097591","https://openalex.org/I1311921367"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111545608","display_name":"J.M. Chin","orcid":null},"institutions":[{"id":"https://openalex.org/I1311921367","display_name":"Advanced Micro Devices (Canada)","ror":"https://ror.org/02yh0k313","country_code":"CA","type":"company","lineage":["https://openalex.org/I1311921367","https://openalex.org/I4210137977"]},{"id":"https://openalex.org/I4210097591","display_name":"Fluidigm (Canada)","ror":"https://ror.org/00xvbmj91","country_code":"CA","type":"company","lineage":["https://openalex.org/I4210097591","https://openalex.org/I922094183"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Jeremy Chin","raw_affiliation_strings":["AMD,CDFX,Markham,Canada"],"affiliations":[{"raw_affiliation_string":"AMD,CDFX,Markham,Canada","institution_ids":["https://openalex.org/I4210097591","https://openalex.org/I1311921367"]}]},{"author_position":"last","author":{"id":null,"display_name":"Katherine Tian","orcid":null},"institutions":[{"id":"https://openalex.org/I4210137977","display_name":"Advanced Micro Devices (United States)","ror":"https://ror.org/04kd6c783","country_code":"US","type":"company","lineage":["https://openalex.org/I4210137977"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Katherine Tian","raw_affiliation_strings":["AMD,CAD,China"],"affiliations":[{"raw_affiliation_string":"AMD,CAD,China","institution_ids":["https://openalex.org/I4210137977"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5091473895"],"corresponding_institution_ids":["https://openalex.org/I1311921367","https://openalex.org/I4210097591"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.34183988,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"414","last_page":"417"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.7272999882698059,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.7272999882698059,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.21570000052452087,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.01889999955892563,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reset","display_name":"Reset (finance)","score":0.6345000267028809},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6122999787330627},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.5164999961853027},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.4465000033378601},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.42559999227523804},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.40560001134872437},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4000000059604645},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.385699987411499},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.3767000138759613}],"concepts":[{"id":"https://openalex.org/C2779795794","wikidata":"https://www.wikidata.org/wiki/Q7315343","display_name":"Reset (finance)","level":2,"score":0.6345000267028809},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6122999787330627},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.5164999961853027},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.48750001192092896},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.48019999265670776},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44999998807907104},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.4465000033378601},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4377000033855438},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.42559999227523804},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.40560001134872437},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.4016000032424927},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4000000059604645},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.385699987411499},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.3767000138759613},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.3752000033855438},{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.3734000027179718},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.3601999878883362},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.33239999413490295},{"id":"https://openalex.org/C2779530757","wikidata":"https://www.wikidata.org/wiki/Q1207505","display_name":"Quality (philosophy)","level":2,"score":0.3212999999523163},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3179999887943268},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3046000003814697},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.29829999804496765},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.2964000105857849},{"id":"https://openalex.org/C7140552","wikidata":"https://www.wikidata.org/wiki/Q1366402","display_name":"Standby power","level":3,"score":0.2808000147342682},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.2727999985218048},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.27160000801086426},{"id":"https://openalex.org/C58140894","wikidata":"https://www.wikidata.org/wiki/Q560398","display_name":"OR gate","level":4,"score":0.2685999870300293},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.2574000060558319},{"id":"https://openalex.org/C141842801","wikidata":"https://www.wikidata.org/wiki/Q363815","display_name":"Automatic test equipment","level":3,"score":0.25600001215934753},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.2517000138759613},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.250900000333786}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/itc58126.2025.00053","is_oa":false,"landing_page_url":"https://doi.org/10.1109/itc58126.2025.00053","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Test Conference (ITC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1983500283","https://openalex.org/W1986876045","https://openalex.org/W2044413944","https://openalex.org/W2048298526","https://openalex.org/W2066558313","https://openalex.org/W2149990012","https://openalex.org/W4206288400","https://openalex.org/W4312700743"],"related_works":[],"abstract_inverted_index":{"Latch":[0],"arrays":[1],"are":[2,123],"increasingly":[3],"popular":[4],"in":[5,32,76],"designs":[6],"due":[7,108],"to":[8,16,45,60,109],"lower":[9],"area":[10,57],"overhead":[11,58],"and":[12,39,92,115,125],"power":[13],"consumption":[14],"compared":[15,59],"the":[17,27,40,53,61,77,99,135],"alternative":[18],"SRAM":[19],"solution.":[20,63,80],"In":[21,64],"this":[22,85],"paper":[23],"we":[24],"will":[25],"visit":[26],"new":[28,137],"scan":[29,138],"strategies":[30,139],"used":[31],"latch":[33,46,96,103,119,129,141],"array":[34,47,97,120,130],"design,":[35],"its":[36],"implementation":[37],"flow,":[38],"benefits":[41],"of":[42,55,102,111],"these":[43],"changes":[44],"test":[48,131],"coverage.":[49],"Scan":[50],"solution":[51],"has":[52],"advantage":[54],"smaller":[56],"BIST":[62,79,106],"addition,":[65],"it":[66],"also":[67],"provides":[68],"failure":[69],"analysis":[70],"capability,":[71],"which":[72],"is":[73,82,132],"not":[74],"available":[75],"traditional":[78],"It":[81],"proven":[83],"that":[84],"innovative":[86],"approach":[87],"could":[88],"achieve":[89],"100%":[90],"SAF":[91],"TDF":[93],"coverage":[94],"for":[95,140],"core.For":[98],"surrounding":[100],"logic":[101,114],"array,":[104],"including":[105],"wrapper,":[107],"complexity":[110],"clock":[112],"gating":[113],"decoding":[116],"logic,":[117],"different":[118],"reset":[121],"schemes":[122],"tested":[124],"compared.":[126],"High":[127],"quality":[128],"achievable":[133],"with":[134],"proposed":[136],"array.":[142]},"counts_by_year":[],"updated_date":"2026-04-21T08:09:41.155169","created_date":"2025-11-03T00:00:00"}
