{"id":"https://openalex.org/W4413755175","doi":"https://doi.org/10.1109/isvlsi65124.2025.11130203","title":"A 4.8ps Resolution, PVT-insensitive Vernier-based TDC using switched-RO PLL and Back Gate Calibration","display_name":"A 4.8ps Resolution, PVT-insensitive Vernier-based TDC using switched-RO PLL and Back Gate Calibration","publication_year":2025,"publication_date":"2025-07-06","ids":{"openalex":"https://openalex.org/W4413755175","doi":"https://doi.org/10.1109/isvlsi65124.2025.11130203"},"language":"en","primary_location":{"id":"doi:10.1109/isvlsi65124.2025.11130203","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi65124.2025.11130203","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5119450514","display_name":"Patroklos Pazionis","orcid":null},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Patroklos Pazionis","raw_affiliation_strings":["ECE, National Technical University of Athens,Athens,Greece"],"affiliations":[{"raw_affiliation_string":"ECE, National Technical University of Athens,Athens,Greece","institution_ids":["https://openalex.org/I174458059"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084023370","display_name":"\u0391\u03bd\u03b4\u03c1\u03ad\u03b1\u03c2 \u03a4\u03c3\u03b9\u03bc\u03c0\u03cc\u03c2","orcid":null},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Andreas Tsimpos","raw_affiliation_strings":["Adveos, Microelectronics,Athens,Greece"],"affiliations":[{"raw_affiliation_string":"Adveos, Microelectronics,Athens,Greece","institution_ids":["https://openalex.org/I4210119392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087127948","display_name":"G. Theodoratos","orcid":"https://orcid.org/0000-0002-2754-7343"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Gerasimos Theodoratos","raw_affiliation_strings":["Adveos, Microelectronics,Athens,Greece"],"affiliations":[{"raw_affiliation_string":"Adveos, Microelectronics,Athens,Greece","institution_ids":["https://openalex.org/I4210119392"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074954167","display_name":"Georgios Panagopoulos","orcid":null},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Georgios Panagopoulos","raw_affiliation_strings":["ECE, National Technical University of Athens,Athens,Greece"],"affiliations":[{"raw_affiliation_string":"ECE, National Technical University of Athens,Athens,Greece","institution_ids":["https://openalex.org/I174458059"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5119450514"],"corresponding_institution_ids":["https://openalex.org/I174458059"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.27096261,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vernier-scale","display_name":"Vernier scale","score":0.8812328577041626},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.6769461631774902},{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.5740979313850403},{"id":"https://openalex.org/keywords/resolution","display_name":"Resolution (logic)","score":0.5572242140769958},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.4761405289173126},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3631710112094879},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.30007416009902954},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.2768457531929016},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.271060049533844},{"id":"https://openalex.org/keywords/optics","display_name":"Optics","score":0.213729590177536},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13468319177627563}],"concepts":[{"id":"https://openalex.org/C69710193","wikidata":"https://www.wikidata.org/wiki/Q14946576","display_name":"Vernier scale","level":2,"score":0.8812328577041626},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.6769461631774902},{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.5740979313850403},{"id":"https://openalex.org/C138268822","wikidata":"https://www.wikidata.org/wiki/Q1051925","display_name":"Resolution (logic)","level":2,"score":0.5572242140769958},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.4761405289173126},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3631710112094879},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.30007416009902954},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.2768457531929016},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.271060049533844},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.213729590177536},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13468319177627563},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvlsi65124.2025.11130203","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi65124.2025.11130203","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.800000011920929,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1508124042","https://openalex.org/W2017690880","https://openalex.org/W2062952706","https://openalex.org/W2084208879","https://openalex.org/W2096434843","https://openalex.org/W2110764323","https://openalex.org/W2111146745","https://openalex.org/W2120912680","https://openalex.org/W2134814047","https://openalex.org/W2136246827","https://openalex.org/W2152144298","https://openalex.org/W2152338756","https://openalex.org/W2163630970","https://openalex.org/W2164582257","https://openalex.org/W2166268103","https://openalex.org/W2607241437","https://openalex.org/W2974142686","https://openalex.org/W3045392656","https://openalex.org/W3169357445","https://openalex.org/W4389855526"],"related_works":["https://openalex.org/W2054844037","https://openalex.org/W2121182846","https://openalex.org/W2069827955","https://openalex.org/W3158414702","https://openalex.org/W3007479161","https://openalex.org/W3083903997","https://openalex.org/W1994021281","https://openalex.org/W2139484866","https://openalex.org/W2107482880","https://openalex.org/W2119823365"],"abstract_inverted_index":{"This":[0,56],"paper":[1],"presents":[2],"a":[3,8,60,72,88,150,166],"robust":[4],"anti-PVT":[5],"mechanism":[6],"for":[7,35,39],"Vernier":[9,82],"Time-to-Digital":[10],"Converter":[11],"(TDC)":[12],"that":[13,63,99],"significantly":[14],"reduces":[15],"resolution":[16,50,143,152],"variations":[17],"due":[18],"to":[19,37],"process,":[20],"voltage,":[21],"and":[22,48,86,133,165],"temperature":[23],"(PVT)":[24],"changes.":[25],"By":[26],"stabilizing":[27],"the":[28,33,44,52,80,102,107,111,116],"resolution,":[29],"our":[30],"approach":[31],"eliminates":[32],"need":[34],"overdesign":[36],"compensate":[38],"reduced":[40],"dynamic":[41],"range":[42],"in":[43,51,79,110],"fast-fast":[45],"(FF)":[46],"corner":[47],"degraded":[49],"slow-slow":[53],"(SS)":[54],"corner.":[55],"is":[57],"achieved":[58],"through":[59],"novel":[61],"architecture":[62],"employs":[64],"two":[65,81],"periodically":[66],"switched":[67],"ring":[68],"oscillators":[69],"(ROs)":[70],"within":[71],"phase-locked":[73],"loop":[74],"(PLL),":[75],"ensuring":[76],"constant":[77],"delays":[78],"Delay":[83],"Lines":[84],"(VDLs)":[85],"maintaining":[87],"fixed":[89],"resolution.":[90],"Additionally,":[91],"we":[92],"propose":[93],"an":[94,141],"optional":[95],"digital":[96],"calibration":[97,128],"technique":[98],"dynamically":[100],"adjusts":[101],"body":[103],"bias":[104],"voltage":[105],"of":[106,119,145,153],"MOS":[108],"transistors":[109],"delay":[112],"elements.":[113],"Implemented":[114],"using":[115],"back-gate":[117],"terminal":[118],"GlobalFoundries\u2019":[120],"22nm":[121],"Fully":[122],"Depleted":[123],"Silicon-On-Insulator":[124],"(FD-SOI)":[125],"technology,":[126],"this":[127],"accelerates":[129],"PLL":[130],"locking":[131],"time":[132],"enhances":[134],"overall":[135],"stability.":[136],"The":[137],"proposed":[138],"scheme":[139],"achieves":[140],"outstanding":[142],"deviation":[144],"just":[146],"0.056":[147],"LSB,":[148],"with":[149],"nominal":[151],"4.8":[154],"ps":[155],"-delivering":[156],"$2":[157],"\\times":[158],"$":[159],"better":[160],"performance":[161],"than":[162],"conventional":[163],"TDCs":[164],"$\\mathbf{5":[167],"0":[168],"\\%}$":[169],"improvement":[170],"over":[171],"state-of-the-art":[172],"designs.":[173]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}