{"id":"https://openalex.org/W4386492666","doi":"https://doi.org/10.1109/isvlsi59464.2023.10238578","title":"Exploiting Routing Asymmetry for APUF Implementation in FPGA: A Proof-of-Concept","display_name":"Exploiting Routing Asymmetry for APUF Implementation in FPGA: A Proof-of-Concept","publication_year":2023,"publication_date":"2023-06-20","ids":{"openalex":"https://openalex.org/W4386492666","doi":"https://doi.org/10.1109/isvlsi59464.2023.10238578"},"language":"en","primary_location":{"id":"doi:10.1109/isvlsi59464.2023.10238578","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi59464.2023.10238578","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071325149","display_name":"Trishna Rajkumar","orcid":"https://orcid.org/0000-0002-1024-7897"},"institutions":[{"id":"https://openalex.org/I86987016","display_name":"KTH Royal Institute of Technology","ror":"https://ror.org/026vcq606","country_code":"SE","type":"education","lineage":["https://openalex.org/I86987016"]}],"countries":["SE"],"is_corresponding":true,"raw_author_name":"Trishna Rajkumar","raw_affiliation_strings":["KTH Royal Institute of Technology,Stockholm,Sweden","KTH Royal Institute of Technology, Stockholm, Sweden"],"affiliations":[{"raw_affiliation_string":"KTH Royal Institute of Technology,Stockholm,Sweden","institution_ids":["https://openalex.org/I86987016"]},{"raw_affiliation_string":"KTH Royal Institute of Technology, Stockholm, Sweden","institution_ids":["https://openalex.org/I86987016"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5071325149"],"corresponding_institution_ids":["https://openalex.org/I86987016"],"apc_list":null,"apc_paid":null,"fwci":0.924,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.71765075,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9925000071525574,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/arbiter","display_name":"Arbiter","score":0.8950730562210083},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8448868989944458},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7460876703262329},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7418239712715149},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.5456968545913696},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.5241910815238953},{"id":"https://openalex.org/keywords/proof-of-concept","display_name":"Proof of concept","score":0.5232402682304382},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.4996523857116699},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.4921678900718689},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.45246952772140503},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.42773985862731934},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4208483099937439},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.4190525710582733},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4097696542739868},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.29122528433799744},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.24425861239433289},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.10261732339859009},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.07946702837944031}],"concepts":[{"id":"https://openalex.org/C2779971761","wikidata":"https://www.wikidata.org/wiki/Q629872","display_name":"Arbiter","level":2,"score":0.8950730562210083},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8448868989944458},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7460876703262329},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7418239712715149},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.5456968545913696},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.5241910815238953},{"id":"https://openalex.org/C124978682","wikidata":"https://www.wikidata.org/wiki/Q1201019","display_name":"Proof of concept","level":2,"score":0.5232402682304382},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.4996523857116699},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.4921678900718689},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.45246952772140503},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.42773985862731934},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4208483099937439},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.4190525710582733},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4097696542739868},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.29122528433799744},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.24425861239433289},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.10261732339859009},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.07946702837944031},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvlsi59464.2023.10238578","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi59464.2023.10238578","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W648862186","https://openalex.org/W1983082199","https://openalex.org/W1990512559","https://openalex.org/W2104401100","https://openalex.org/W2129720900","https://openalex.org/W3022312380","https://openalex.org/W3196238133","https://openalex.org/W4212790135","https://openalex.org/W4224098347","https://openalex.org/W4296558705","https://openalex.org/W6810719823"],"related_works":["https://openalex.org/W2535403365","https://openalex.org/W1486911645","https://openalex.org/W1931527840","https://openalex.org/W2132668926","https://openalex.org/W2091330445","https://openalex.org/W4393106778","https://openalex.org/W2135304146","https://openalex.org/W2476941693","https://openalex.org/W4285297227","https://openalex.org/W4231811236"],"abstract_inverted_index":{"Implementing":[0],"Arbiter":[1],"PUF":[2,101],"in":[3],"an":[4,74,99],"FPGA":[5,24,35,79,105],"requires":[6,38],"identical":[7],"logic":[8],"and":[9,30,43,68,131],"symmetrical":[10],"routing":[11,25,42,111],"to":[12,19,54,87],"ensure":[13],"the":[14,23,34,44,78,96,104,110],"delay":[15],"differences":[16],"are":[17],"due":[18],"process":[20],"variations.":[21],"As":[22],"tools":[26],"optimise":[27],"for":[28,32],"performance":[29],"not":[31,83],"symmetry,":[33],"CAD":[36,106],"flow":[37,107],"interventions":[39],"like":[40],"manual":[41],"use":[45],"of":[46,60,77,98,114,119,122,128,133],"hard":[47],"macros.":[48],"These":[49],"measures":[50],"require":[51,73],"a":[52,57,120],"designer":[53],"work":[55],"at":[56],"lower":[58],"level":[59],"abstraction":[61],"than":[62],"RTL":[63],"which":[64,81],"can":[65],"be":[66,84],"tedious":[67],"error":[69],"prone.":[70],"Furthermore,":[71],"they":[72],"extensive":[75],"knowledge":[76],"fabric":[80],"may":[82],"available":[85],"owing":[86],"their":[88],"proprietary":[89],"nature.":[90],"Considering":[91],"these":[92],"challenges,":[93],"we":[94],"investigate":[95],"possibility":[97],"arbiter":[100],"implementation":[102],"within":[103],"by":[108],"leveraging":[109],"asymmetry":[112],"instead":[113],"eliminating":[115],"it.":[116],"Preliminary":[117],"characterisation":[118],"proof":[121],"concept":[123],"APUF":[124],"model":[125],"demonstrated":[126],"uniformity":[127],"49.4":[129],"%":[130],"reliability":[132],"96.3":[134],"%.":[135]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
