{"id":"https://openalex.org/W2762416833","doi":"https://doi.org/10.1109/isvdat.2016.8064899","title":"Quantification of figures of merit of 7T and 8T SRAM cells in subthreshold region and their comparison with the conventional 6T SRAM cell","display_name":"Quantification of figures of merit of 7T and 8T SRAM cells in subthreshold region and their comparison with the conventional 6T SRAM cell","publication_year":2016,"publication_date":"2016-05-01","ids":{"openalex":"https://openalex.org/W2762416833","doi":"https://doi.org/10.1109/isvdat.2016.8064899","mag":"2762416833"},"language":"en","primary_location":{"id":"doi:10.1109/isvdat.2016.8064899","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2016.8064899","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101783272","display_name":"Pulkit Sharma","orcid":"https://orcid.org/0000-0001-7870-7098"},"institutions":[{"id":"https://openalex.org/I119939252","display_name":"Indraprastha Institute of Information Technology Delhi","ror":"https://ror.org/03vfp4g33","country_code":"IN","type":"education","lineage":["https://openalex.org/I119939252"]},{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Pulkit Sharma","raw_affiliation_strings":["ECE Department, IIIT, Delhi, India"],"affiliations":[{"raw_affiliation_string":"ECE Department, IIIT, Delhi, India","institution_ids":["https://openalex.org/I119939252","https://openalex.org/I68891433"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078619375","display_name":"Raghupatruni Anusha","orcid":null},"institutions":[{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]},{"id":"https://openalex.org/I119939252","display_name":"Indraprastha Institute of Information Technology Delhi","ror":"https://ror.org/03vfp4g33","country_code":"IN","type":"education","lineage":["https://openalex.org/I119939252"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"R. Anusha","raw_affiliation_strings":["ECE Department, IIIT, Delhi, India"],"affiliations":[{"raw_affiliation_string":"ECE Department, IIIT, Delhi, India","institution_ids":["https://openalex.org/I119939252","https://openalex.org/I68891433"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108650405","display_name":"Krishna Bharath","orcid":null},"institutions":[{"id":"https://openalex.org/I119939252","display_name":"Indraprastha Institute of Information Technology Delhi","ror":"https://ror.org/03vfp4g33","country_code":"IN","type":"education","lineage":["https://openalex.org/I119939252"]},{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"K. Bharath","raw_affiliation_strings":["ECE Department, IIIT, Delhi, India"],"affiliations":[{"raw_affiliation_string":"ECE Department, IIIT, Delhi, India","institution_ids":["https://openalex.org/I119939252","https://openalex.org/I68891433"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027387162","display_name":"Jasmine Kaur Gulati","orcid":null},"institutions":[{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]},{"id":"https://openalex.org/I119939252","display_name":"Indraprastha Institute of Information Technology Delhi","ror":"https://ror.org/03vfp4g33","country_code":"IN","type":"education","lineage":["https://openalex.org/I119939252"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Jasmine K. Gulati","raw_affiliation_strings":["ECE Department, IIIT, Delhi, India"],"affiliations":[{"raw_affiliation_string":"ECE Department, IIIT, Delhi, India","institution_ids":["https://openalex.org/I119939252","https://openalex.org/I68891433"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077692941","display_name":"Preet K. Walia","orcid":null},"institutions":[{"id":"https://openalex.org/I119939252","display_name":"Indraprastha Institute of Information Technology Delhi","ror":"https://ror.org/03vfp4g33","country_code":"IN","type":"education","lineage":["https://openalex.org/I119939252"]},{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Preet K. Walia","raw_affiliation_strings":["ECE Department, IIIT, Delhi, India"],"affiliations":[{"raw_affiliation_string":"ECE Department, IIIT, Delhi, India","institution_ids":["https://openalex.org/I119939252","https://openalex.org/I68891433"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084951491","display_name":"Sumit J. Darak","orcid":"https://orcid.org/0000-0001-8656-4533"},"institutions":[{"id":"https://openalex.org/I119939252","display_name":"Indraprastha Institute of Information Technology Delhi","ror":"https://ror.org/03vfp4g33","country_code":"IN","type":"education","lineage":["https://openalex.org/I119939252"]},{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sumit J. Darak","raw_affiliation_strings":["ECE Department, IIIT, Delhi, India"],"affiliations":[{"raw_affiliation_string":"ECE Department, IIIT, Delhi, India","institution_ids":["https://openalex.org/I119939252","https://openalex.org/I68891433"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5101783272"],"corresponding_institution_ids":["https://openalex.org/I119939252","https://openalex.org/I68891433"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.22704508,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.9228969812393188},{"id":"https://openalex.org/keywords/subthreshold-conduction","display_name":"Subthreshold conduction","score":0.8357342481613159},{"id":"https://openalex.org/keywords/figure-of-merit","display_name":"Figure of merit","score":0.7947104573249817},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6147134304046631},{"id":"https://openalex.org/keywords/margin","display_name":"Margin (machine learning)","score":0.5520173907279968},{"id":"https://openalex.org/keywords/parametric-statistics","display_name":"Parametric statistics","score":0.5028504729270935},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.48348838090896606},{"id":"https://openalex.org/keywords/noise-margin","display_name":"Noise margin","score":0.4834200143814087},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.47138863801956177},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4372893273830414},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.4107098877429962},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.34436744451522827},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21888110041618347},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18114137649536133},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1546144187450409},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.1199488639831543},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.0714946985244751}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.9228969812393188},{"id":"https://openalex.org/C156465305","wikidata":"https://www.wikidata.org/wiki/Q1658601","display_name":"Subthreshold conduction","level":4,"score":0.8357342481613159},{"id":"https://openalex.org/C130277099","wikidata":"https://www.wikidata.org/wiki/Q3676605","display_name":"Figure of merit","level":2,"score":0.7947104573249817},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6147134304046631},{"id":"https://openalex.org/C774472","wikidata":"https://www.wikidata.org/wiki/Q6760393","display_name":"Margin (machine learning)","level":2,"score":0.5520173907279968},{"id":"https://openalex.org/C117251300","wikidata":"https://www.wikidata.org/wiki/Q1849855","display_name":"Parametric statistics","level":2,"score":0.5028504729270935},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.48348838090896606},{"id":"https://openalex.org/C179499742","wikidata":"https://www.wikidata.org/wiki/Q1324892","display_name":"Noise margin","level":4,"score":0.4834200143814087},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.47138863801956177},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4372893273830414},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.4107098877429962},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.34436744451522827},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21888110041618347},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18114137649536133},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1546144187450409},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.1199488639831543},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0714946985244751},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvdat.2016.8064899","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2016.8064899","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.49000000953674316,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2078783751","https://openalex.org/W2542332651"],"related_works":["https://openalex.org/W2117824263","https://openalex.org/W2134421493","https://openalex.org/W3086682201","https://openalex.org/W2743772479","https://openalex.org/W2118528827","https://openalex.org/W2154145758","https://openalex.org/W2110839220","https://openalex.org/W2775062502","https://openalex.org/W2044270051","https://openalex.org/W1544650831"],"abstract_inverted_index":{"The":[0,45],"need":[1],"for":[2],"low-power":[3],"SRAM":[4,21,49],"results":[5],"in":[6,10,24,29,79,82],"many":[7],"design":[8],"challenges":[9],"deep":[11],"submicron":[12],"technology.":[13],"In":[14],"this":[15],"paper,":[16],"6T,":[17],"7T":[18,46],"and":[19,47,71],"8T":[20,48,58],"cells":[22,50,77],"designed":[23],"65nm":[25],"bulk":[26],"CMOS":[27],"technology":[28],"the":[30,37,83,94],"subthreshold":[31,84],"region":[32],"have":[33],"been":[34,89],"compared":[35],"on":[36,96],"basis":[38],"of":[39,42],"various":[40],"Figures":[41],"Merit":[43],"(FoMs).":[44],"are":[51],"able":[52],"to":[53,92,99],"work":[54],"at":[55],"200mV":[56],"with":[57],"exhibiting":[59],"highest":[60],"Read":[61],"Static":[62,67],"Noise":[63,68,73],"Margin":[64,69,74],"(RSNM),":[65],"Hold":[66],"(HSNM)":[70],"Write":[72],"(WNM).":[75],"All":[76],"result":[78],"low":[80],"leakage":[81],"region.":[85],"Statistical":[86],"Analysis":[87],"has":[88],"carried":[90],"out":[91],"examine":[93],"effect":[95],"RSNM":[97],"due":[98],"on-die":[100],"parametric":[101],"fluctuations.":[102]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}