{"id":"https://openalex.org/W2761605584","doi":"https://doi.org/10.1109/isvdat.2016.8064881","title":"On determination of instantaneous peak and cycle peak switching using ILP","display_name":"On determination of instantaneous peak and cycle peak switching using ILP","publication_year":2016,"publication_date":"2016-05-01","ids":{"openalex":"https://openalex.org/W2761605584","doi":"https://doi.org/10.1109/isvdat.2016.8064881","mag":"2761605584"},"language":"en","primary_location":{"id":"doi:10.1109/isvdat.2016.8064881","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2016.8064881","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5018402972","display_name":"Rohini Gulve","orcid":null},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Rohini Gulve","raw_affiliation_strings":["Computer Architecture and Dependable systems Lab, Electrical Engineering, Indian Institute of Technology Bombay, India"],"affiliations":[{"raw_affiliation_string":"Computer Architecture and Dependable systems Lab, Electrical Engineering, Indian Institute of Technology Bombay, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055856021","display_name":"Nihar Hage","orcid":null},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Nihar Hage","raw_affiliation_strings":["Computer Architecture and Dependable systems Lab, Electrical Engineering, Indian Institute of Technology Bombay, India"],"affiliations":[{"raw_affiliation_string":"Computer Architecture and Dependable systems Lab, Electrical Engineering, Indian Institute of Technology Bombay, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018584319","display_name":"Jaynarayan Tudu","orcid":"https://orcid.org/0000-0002-0329-3190"},"institutions":[{"id":"https://openalex.org/I59270414","display_name":"Indian Institute of Science Bangalore","ror":"https://ror.org/04dese585","country_code":"IN","type":"education","lineage":["https://openalex.org/I59270414"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Jaynarayan Tudu","raw_affiliation_strings":["Computer Science and Automation, Indian Institute of Science Bangalore, India"],"affiliations":[{"raw_affiliation_string":"Computer Science and Automation, Indian Institute of Science Bangalore, India","institution_ids":["https://openalex.org/I59270414"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5018402972"],"corresponding_institution_ids":["https://openalex.org/I162827531"],"apc_list":null,"apc_paid":null,"fwci":0.3675,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.68716274,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":"51","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5816985368728638},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5212819576263428},{"id":"https://openalex.org/keywords/instant","display_name":"Instant","score":0.4680817723274231},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4617294371128082},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.423241525888443},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.4107188880443573},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.37192004919052124},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3640751242637634},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3584769666194916},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22583317756652832},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.21849021315574646},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.17134630680084229}],"concepts":[{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5816985368728638},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5212819576263428},{"id":"https://openalex.org/C2779432360","wikidata":"https://www.wikidata.org/wiki/Q16963779","display_name":"Instant","level":2,"score":0.4680817723274231},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4617294371128082},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.423241525888443},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.4107188880443573},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.37192004919052124},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3640751242637634},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3584769666194916},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22583317756652832},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.21849021315574646},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.17134630680084229},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvdat.2016.8064881","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2016.8064881","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.7799999713897705,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320323448","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W64155922","https://openalex.org/W1595368737","https://openalex.org/W1948704692","https://openalex.org/W2008823100","https://openalex.org/W2013085877","https://openalex.org/W2096424065","https://openalex.org/W2129718124","https://openalex.org/W2135159456","https://openalex.org/W2142304312","https://openalex.org/W2149396421","https://openalex.org/W6681844034"],"related_works":["https://openalex.org/W2356370096","https://openalex.org/W2794694000","https://openalex.org/W2094154142","https://openalex.org/W2350999733","https://openalex.org/W2392387319","https://openalex.org/W2359725054","https://openalex.org/W4287262429","https://openalex.org/W4287262247","https://openalex.org/W4287613691","https://openalex.org/W2774547058"],"abstract_inverted_index":{"Power":[0,13,67],"has":[1],"becomes":[2],"one":[3],"of":[4,15,25,64,85,112,122,174,187,200],"the":[5,65,86,108,141,162,166,172,184,197],"crucial":[6],"parameter":[7],"while":[8],"designing":[9],"a":[10,16,41,157],"SOC":[11],"ICs.":[12],"analysis":[14,181],"circuit":[17,70,142],"is":[18,71,98],"important":[19],"for":[20,136],"reliability":[21],"check,":[22],"better":[23],"design":[24],"power":[26,34,48],"distribution":[27],"network,":[28],"packaging":[29],"decisions":[30],"and":[31,79,196],"to":[32,60,73],"solve":[33],"issues":[35],"during":[36,150,177,205],"test.":[37],"High":[38],"switching":[39,74,90,117],"at":[40,76,107,119,143,192],"time":[42,110,123,146,194],"demands":[43],"high":[44],"instantaneous":[45],"current":[46],"from":[47],"supply":[49],"network.":[50],"Which":[51],"gates":[52,103,189,202],"experience":[53],"V":[54],"<sub":[55],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[56],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">dd</sub>":[57],"drop":[58],"leading":[59],"increase":[61],"in":[62,140,165],"delay":[63],"circuit.":[66,167],"consumed":[68],"by":[69],"proportional":[72],"activity":[75,91,164],"gate":[77],"outputs":[78],"capacitance":[80],"associated":[81,113],"with":[82],"it.":[83],"Most":[84],"previous":[87],"work":[88],"consider":[89],"over":[92],"entire":[93,151],"clock":[94,152,206],"period,":[95],"however":[96],"this":[97,128],"very":[99],"pessimistic":[100],"approach.":[101],"All":[102],"do":[104],"not":[105],"switch":[106,191,204],"same":[109],"because":[111],"delays,":[114],"thus":[115],"peak":[116],"occurring":[118,176],"an":[120,132],"instant":[121,145,195],"should":[124],"be":[125],"considered.":[126],"In":[127],"paper":[129],"we":[130],"formulate":[131],"Integer":[133],"Linear":[134],"Programming":[135],"computing":[137],"maximum":[138,185,198],"transitions":[139],"any":[144,193],"as":[147,149],"well":[148],"period.":[153,207],"This":[154],"method":[155,170],"identifies":[156],"vector":[158],"pair":[159],"which":[160],"provides":[161],"highest":[163],"The":[168],"proposed":[169],"captures":[171],"impact":[173],"glitches":[175],"signal":[178],"propagation.":[179],"Our":[180],"shows":[182],"that":[183],"75%":[186],"total":[188,201],"can":[190,203],"625%":[199]},"counts_by_year":[{"year":2017,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}