{"id":"https://openalex.org/W1556370277","doi":"https://doi.org/10.1109/isvdat.2015.7208130","title":"PDF testability of a combinational circuit derived by covering ROBDD nodes using Invert-And-Or circuits","display_name":"PDF testability of a combinational circuit derived by covering ROBDD nodes using Invert-And-Or circuits","publication_year":2015,"publication_date":"2015-06-01","ids":{"openalex":"https://openalex.org/W1556370277","doi":"https://doi.org/10.1109/isvdat.2015.7208130","mag":"1556370277"},"language":"en","primary_location":{"id":"doi:10.1109/isvdat.2015.7208130","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2015.7208130","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 19th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5045092501","display_name":"Toral Shah","orcid":"https://orcid.org/0000-0003-4037-2418"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Toral Shah","raw_affiliation_strings":["IIT Bombay, India","IIT Bombay, INDIA#TAB#"],"affiliations":[{"raw_affiliation_string":"IIT Bombay, India","institution_ids":["https://openalex.org/I162827531"]},{"raw_affiliation_string":"IIT Bombay, INDIA#TAB#","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059600435","display_name":"A. Matrosova","orcid":"https://orcid.org/0000-0002-8662-4740"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Anzhela Matrosova","raw_affiliation_strings":["Tomsk Sate University, Russia"],"affiliations":[{"raw_affiliation_string":"Tomsk Sate University, Russia","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073587430","display_name":"Virendra Singh","orcid":"https://orcid.org/0000-0002-7035-7844"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Virendra Singh","raw_affiliation_strings":["IIT Bombay, India","IIT Bombay, INDIA#TAB#"],"affiliations":[{"raw_affiliation_string":"IIT Bombay, India","institution_ids":["https://openalex.org/I162827531"]},{"raw_affiliation_string":"IIT Bombay, INDIA#TAB#","institution_ids":["https://openalex.org/I162827531"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5045092501"],"corresponding_institution_ids":["https://openalex.org/I162827531"],"apc_list":null,"apc_paid":null,"fwci":0.646,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.67180319,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"23","issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.7456221580505371},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.7413819432258606},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6467674374580383},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.6213870048522949},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.5660318732261658},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4277176558971405},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4267627000808716},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.42334187030792236},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.41082414984703064},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.34956634044647217},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.15555578470230103},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13414108753204346}],"concepts":[{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.7456221580505371},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.7413819432258606},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6467674374580383},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.6213870048522949},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.5660318732261658},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4277176558971405},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4267627000808716},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.42334187030792236},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.41082414984703064},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.34956634044647217},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.15555578470230103},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13414108753204346},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvdat.2015.7208130","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2015.7208130","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 19th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2024632819","https://openalex.org/W2096785857","https://openalex.org/W6656470888"],"related_works":["https://openalex.org/W2168652618","https://openalex.org/W29481652","https://openalex.org/W2069145203","https://openalex.org/W2085176210","https://openalex.org/W1702800398","https://openalex.org/W2106889348","https://openalex.org/W2083793411","https://openalex.org/W2135500595","https://openalex.org/W2427864131","https://openalex.org/W2127247647"],"abstract_inverted_index":{"For":[0],"high":[1],"end":[2],"design,":[3],"delay":[4,17],"test":[5],"becomes":[6],"increasingly":[7],"important.":[8],"The":[9],"paper":[10],"proposes":[11],"a":[12],"technique":[13],"to":[14],"synthesize":[15],"fully":[16,45],"testable":[18,46],"circuit":[19,43],"without":[20],"any":[21],"additional":[22],"control":[23],"input.":[24],"Our":[25],"proposal":[26],"is":[27,44],"based":[28],"on":[29],"covering":[30],"each":[31],"ROBDD":[32],"node":[33],"by":[34,48,52],"Invert-And-Or":[35],"elements.":[36],"We":[37],"have":[38],"shown":[39],"that":[40],"the":[41],"generated":[42],"either":[47],"robust":[49],"tests":[50],"or":[51],"validatable":[53],"non-robust":[54],"tests.":[55]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
