{"id":"https://openalex.org/W1531221997","doi":"https://doi.org/10.1109/isvdat.2015.7208126","title":"Modified low power scan based technique","display_name":"Modified low power scan based technique","publication_year":2015,"publication_date":"2015-06-01","ids":{"openalex":"https://openalex.org/W1531221997","doi":"https://doi.org/10.1109/isvdat.2015.7208126","mag":"1531221997"},"language":"en","primary_location":{"id":"doi:10.1109/isvdat.2015.7208126","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2015.7208126","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 19th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010820868","display_name":"M.R. Gowthami","orcid":null},"institutions":[{"id":"https://openalex.org/I70699430","display_name":"Utkal University","ror":"https://ror.org/0034eez47","country_code":"IN","type":"education","lineage":["https://openalex.org/I70699430"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"M R Gowthami","raw_affiliation_strings":["VLSI Dept., UTL technologies LTD., Bangalore, India","VLSI Dept., VTU Extension Centre, UTL technologies LTD., Bangalore, India"],"affiliations":[{"raw_affiliation_string":"VLSI Dept., UTL technologies LTD., Bangalore, India","institution_ids":["https://openalex.org/I70699430"]},{"raw_affiliation_string":"VLSI Dept., VTU Extension Centre, UTL technologies LTD., Bangalore, India","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028258971","display_name":"G. Harish","orcid":null},"institutions":[{"id":"https://openalex.org/I70699430","display_name":"Utkal University","ror":"https://ror.org/0034eez47","country_code":"IN","type":"education","lineage":["https://openalex.org/I70699430"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"G. Harish","raw_affiliation_strings":["VLSI Dept., UTL technologies LTD., Bangalore, India","VLSI Dept., VTU Extension Centre, UTL technologies LTD., Bangalore, India"],"affiliations":[{"raw_affiliation_string":"VLSI Dept., UTL technologies LTD., Bangalore, India","institution_ids":["https://openalex.org/I70699430"]},{"raw_affiliation_string":"VLSI Dept., VTU Extension Centre, UTL technologies LTD., Bangalore, India","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087000420","display_name":"B.V. Bhargav Ram","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"B V Bhargav Ram","raw_affiliation_strings":["VLSI Dept., VTU Extension Centre, UTL technologies LTD., Bangalore, India"],"affiliations":[{"raw_affiliation_string":"VLSI Dept., VTU Extension Centre, UTL technologies LTD., Bangalore, India","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076480907","display_name":"Siva Yellampalli","orcid":"https://orcid.org/0000-0001-6774-1514"},"institutions":[{"id":"https://openalex.org/I70699430","display_name":"Utkal University","ror":"https://ror.org/0034eez47","country_code":"IN","type":"education","lineage":["https://openalex.org/I70699430"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Siva Yellampalli","raw_affiliation_strings":["VLSI Dept., UTL technologies LTD., Bangalore, India","VLSI Dept., VTU Extension Centre, UTL technologies LTD., Bangalore, India"],"affiliations":[{"raw_affiliation_string":"VLSI Dept., UTL technologies LTD., Bangalore, India","institution_ids":["https://openalex.org/I70699430"]},{"raw_affiliation_string":"VLSI Dept., VTU Extension Centre, UTL technologies LTD., Bangalore, India","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5010820868"],"corresponding_institution_ids":["https://openalex.org/I70699430"],"apc_list":null,"apc_paid":null,"fwci":0.3318,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.57292485,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.8989853262901306},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6810086965560913},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.6729167699813843},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6586949825286865},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6021401882171631},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5829235315322876},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.537199079990387},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.5280659198760986},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5231857895851135},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4549647271633148},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.4346621334552765},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.43256521224975586},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.4132637083530426},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3873698115348816},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3402259051799774},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3252090811729431},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.272308886051178},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2075963020324707},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.1718716323375702},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14454272389411926},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.13449335098266602},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08146539330482483}],"concepts":[{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.8989853262901306},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6810086965560913},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.6729167699813843},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6586949825286865},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6021401882171631},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5829235315322876},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.537199079990387},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.5280659198760986},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5231857895851135},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4549647271633148},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.4346621334552765},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.43256521224975586},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.4132637083530426},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3873698115348816},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3402259051799774},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3252090811729431},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.272308886051178},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2075963020324707},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.1718716323375702},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14454272389411926},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.13449335098266602},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08146539330482483},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvdat.2015.7208126","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2015.7208126","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 19th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.5899999737739563}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W53227076","https://openalex.org/W197391467","https://openalex.org/W1496730449","https://openalex.org/W2131943868","https://openalex.org/W2135615172","https://openalex.org/W2146893269","https://openalex.org/W2149690470","https://openalex.org/W2168755502","https://openalex.org/W2553126414","https://openalex.org/W3203992401","https://openalex.org/W4239375888","https://openalex.org/W6602153322","https://openalex.org/W6607990715","https://openalex.org/W6629844068","https://openalex.org/W6656594533","https://openalex.org/W6681451533","https://openalex.org/W6729967060"],"related_works":["https://openalex.org/W1581610324","https://openalex.org/W2129124567","https://openalex.org/W2167571917","https://openalex.org/W3088373974","https://openalex.org/W2620614665","https://openalex.org/W2146547687","https://openalex.org/W2049913894","https://openalex.org/W2146381271","https://openalex.org/W2801332551","https://openalex.org/W2127184179"],"abstract_inverted_index":{"The":[0,65],"testing":[1,11,14],"power":[2,15,22,35,73,106,111],"is":[3,16,37,68],"the":[4,13,20,25,28,41,49,57,63,76,87,95,102,109],"biggest":[5],"concern":[6],"in":[7,43,71,81,90],"modern":[8],"VLSI":[9],"chip":[10],"as":[12,75],"very":[17,69],"greater":[18],"than":[19],"functional":[21],"which":[23,39,85],"affects":[24],"reliability":[26],"of":[27],"chip.":[29],"In":[30],"this":[31],"paper":[32],"low":[33,104],"test":[34,72,105,110,116],"architecture":[36,107],"proposed":[38,66,103],"loads":[40],"pattern":[42],"one":[44,61,82],"scan":[45,51,59,83,92],"chain":[46,60,84],"serially":[47],"and":[48],"rest":[50],"chains":[52],"are":[53],"loaded":[54],"parallel":[55],"by":[56,112],"serial":[58,77],"after":[62],"other.":[64],"technique":[67],"effective":[70],"reduction":[74],"shifting":[78],"happens":[79],"only":[80],"reduces":[86,108],"switching":[88],"activity":[89],"other":[91],"chains.":[93],"From":[94],"experiments":[96],"conducted":[97],"on":[98],"ISCAS89":[99],"benchmark":[100],"circuits,":[101],"65%":[113],"with":[114],"additional":[115],"cycles.":[117]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2016,"cited_by_count":1}],"updated_date":"2026-03-21T08:13:44.787528","created_date":"2025-10-10T00:00:00"}