{"id":"https://openalex.org/W1537313130","doi":"https://doi.org/10.1109/isvdat.2015.7208069","title":"A 4 bit medium speed flash ADC using inverter based comparator in 0.18&amp;#x03BC;m CMOS","display_name":"A 4 bit medium speed flash ADC using inverter based comparator in 0.18&amp;#x03BC;m CMOS","publication_year":2015,"publication_date":"2015-06-01","ids":{"openalex":"https://openalex.org/W1537313130","doi":"https://doi.org/10.1109/isvdat.2015.7208069","mag":"1537313130"},"language":"en","primary_location":{"id":"doi:10.1109/isvdat.2015.7208069","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2015.7208069","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 19th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078679232","display_name":"D. Malathi","orcid":null},"institutions":[{"id":"https://openalex.org/I122964287","display_name":"National Institute of Technology Tiruchirappalli","ror":"https://ror.org/047x65e68","country_code":"IN","type":"education","lineage":["https://openalex.org/I122964287"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"D. Malathi","raw_affiliation_strings":["Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirapalli, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirapalli, India","institution_ids":["https://openalex.org/I122964287"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026721694","display_name":"R. Greeshma","orcid":null},"institutions":[{"id":"https://openalex.org/I122964287","display_name":"National Institute of Technology Tiruchirappalli","ror":"https://ror.org/047x65e68","country_code":"IN","type":"education","lineage":["https://openalex.org/I122964287"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"R. Greeshma","raw_affiliation_strings":["Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirapalli, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirapalli, India","institution_ids":["https://openalex.org/I122964287"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050411721","display_name":"R. Sanjay","orcid":null},"institutions":[{"id":"https://openalex.org/I122964287","display_name":"National Institute of Technology Tiruchirappalli","ror":"https://ror.org/047x65e68","country_code":"IN","type":"education","lineage":["https://openalex.org/I122964287"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"R. Sanjay","raw_affiliation_strings":["Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirapalli, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirapalli, India","institution_ids":["https://openalex.org/I122964287"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018233463","display_name":"B. Venkataramani","orcid":null},"institutions":[{"id":"https://openalex.org/I122964287","display_name":"National Institute of Technology Tiruchirappalli","ror":"https://ror.org/047x65e68","country_code":"IN","type":"education","lineage":["https://openalex.org/I122964287"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"B. Venkataramani","raw_affiliation_strings":["Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirapalli, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirapalli, India","institution_ids":["https://openalex.org/I122964287"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5078679232"],"corresponding_institution_ids":["https://openalex.org/I122964287"],"apc_list":null,"apc_paid":null,"fwci":0.7081,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.69691121,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.9670661091804504},{"id":"https://openalex.org/keywords/effective-number-of-bits","display_name":"Effective number of bits","score":0.8456588387489319},{"id":"https://openalex.org/keywords/flash-adc","display_name":"Flash ADC","score":0.8415902853012085},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7121735215187073},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.6436346769332886},{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.5776491761207581},{"id":"https://openalex.org/keywords/least-significant-bit","display_name":"Least significant bit","score":0.5511366128921509},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5147628784179688},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4914904832839966},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4498259425163269},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4262693524360657},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.42589202523231506},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2610322833061218}],"concepts":[{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.9670661091804504},{"id":"https://openalex.org/C16671190","wikidata":"https://www.wikidata.org/wiki/Q505579","display_name":"Effective number of bits","level":3,"score":0.8456588387489319},{"id":"https://openalex.org/C164862427","wikidata":"https://www.wikidata.org/wiki/Q2744647","display_name":"Flash ADC","level":4,"score":0.8415902853012085},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7121735215187073},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.6436346769332886},{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.5776491761207581},{"id":"https://openalex.org/C4305246","wikidata":"https://www.wikidata.org/wiki/Q3885225","display_name":"Least significant bit","level":2,"score":0.5511366128921509},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5147628784179688},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4914904832839966},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4498259425163269},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4262693524360657},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.42589202523231506},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2610322833061218},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvdat.2015.7208069","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2015.7208069","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 19th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W156735343","https://openalex.org/W1496153961","https://openalex.org/W1979798093","https://openalex.org/W1981151840","https://openalex.org/W2022439183","https://openalex.org/W2060869465","https://openalex.org/W2062398121","https://openalex.org/W2064936019","https://openalex.org/W2091117344","https://openalex.org/W2098886382","https://openalex.org/W2105233835","https://openalex.org/W2108505754","https://openalex.org/W2139425536","https://openalex.org/W2141433154","https://openalex.org/W2751995795","https://openalex.org/W6674839944","https://openalex.org/W6675892439"],"related_works":["https://openalex.org/W2914701507","https://openalex.org/W2905521207","https://openalex.org/W2168717468","https://openalex.org/W2079575076","https://openalex.org/W2075144748","https://openalex.org/W3156142317","https://openalex.org/W2593119273","https://openalex.org/W2161345192","https://openalex.org/W2104938423","https://openalex.org/W3009658300"],"abstract_inverted_index":{"Inverter":[0],"based":[1,55],"comparators":[2],"are":[3],"proposed":[4,64,101,118,149,161],"in":[5,26,65,105,157],"the":[6,30,33,43,46,100,148,158],"literature":[7],"for":[8,128],"medium":[9],"speed":[10,44],"ADCs":[11],"with":[12,84,132],"low":[13,16],"power":[14,85,139,145],"and":[15,77,136,176],"area":[17],"requirements.":[18],"The":[19,68,117,144,160],"comparator":[20,56],"is":[21,63,71,103,151],"succeeded":[22],"by":[23,147],"a":[24,52,59,96,111,121,138,183],"buffer":[25],"order":[27],"to":[28,73,79,88,154],"boost":[29],"gain":[31],"of":[32,45,114,125,141,165,169,173,186],"comparator.":[34],"This":[35],"requires":[36],"an":[37,129],"additional":[38],"delayed":[39],"clock":[40,61],"which":[41,57],"limits":[42],"ADC.":[47],"To":[48],"overcome":[49],"this":[50,66],"limitation,":[51],"modified":[53],"inverter":[54],"uses":[58],"single":[60],"signal":[62,131],"paper.":[67],"analog":[69],"input":[70,130],"converted":[72],"gray":[74],"codes":[75],"first":[76],"then":[78],"binary":[80,89],"codes.":[81],"It":[82,181],"dispenses":[83],"hungry":[86],"thermometer":[87],"code":[90],"converter.":[91],"For":[92],"evaluating":[93],"its":[94],"efficacy,":[95],"4-bit":[97],"ADC":[98,119,150,162],"using":[99],"technique":[102],"implemented":[104],"UMC":[106],"0.18\u03bcm":[107],"CMOS":[108],"technology":[109],"at":[110],"supply":[112],"voltage":[113],"1.8":[115,133],"V.":[116],"achieves":[120],"maximum":[122],"sampling":[123],"rate":[124],"100":[126],"MS/s":[127],"V":[134],"swing":[135],"has":[137,182],"consumption":[140],"1.08":[142],"mW.":[143],"dissipated":[146],"lower":[152],"compared":[153],"those":[155],"reported":[156],"literature.":[159],"exhibits":[163],"INL":[164],"1.36":[166],"LSB,":[167,171],"DNL":[168],"1.04":[170],"SNDR":[172],"23.59":[174],"dB":[175],"ENOB":[177],"3.62":[178],"bits":[179],"respectively.":[180],"better":[184],"FoM":[185],"0.87":[187],"pJ/conversion":[188],"step.":[189]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
