{"id":"https://openalex.org/W1546614846","doi":"https://doi.org/10.1109/isvdat.2015.7208068","title":"C<sup>2</sup>-DLM: Cache coherence aware dual link mesh for on-chip interconnect","display_name":"C<sup>2</sup>-DLM: Cache coherence aware dual link mesh for on-chip interconnect","publication_year":2015,"publication_date":"2015-06-01","ids":{"openalex":"https://openalex.org/W1546614846","doi":"https://doi.org/10.1109/isvdat.2015.7208068","mag":"1546614846"},"language":"en","primary_location":{"id":"doi:10.1109/isvdat.2015.7208068","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2015.7208068","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 19th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054487156","display_name":"Sonal Yadav","orcid":"https://orcid.org/0000-0002-0608-567X"},"institutions":[{"id":"https://openalex.org/I83205935","display_name":"Malaviya National Institute of Technology Jaipur","ror":"https://ror.org/0077k1j32","country_code":"IN","type":"education","lineage":["https://openalex.org/I83205935"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Sonal Yadav","raw_affiliation_strings":["MNIT, Jaipur, India"],"affiliations":[{"raw_affiliation_string":"MNIT, Jaipur, India","institution_ids":["https://openalex.org/I83205935"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087820056","display_name":"Vijay Laxmi","orcid":"https://orcid.org/0000-0002-3662-8487"},"institutions":[{"id":"https://openalex.org/I83205935","display_name":"Malaviya National Institute of Technology Jaipur","ror":"https://ror.org/0077k1j32","country_code":"IN","type":"education","lineage":["https://openalex.org/I83205935"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"V. Laxmi","raw_affiliation_strings":["MNIT, Jaipur, India"],"affiliations":[{"raw_affiliation_string":"MNIT, Jaipur, India","institution_ids":["https://openalex.org/I83205935"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028420263","display_name":"Manoj Singh Gaur","orcid":"https://orcid.org/0000-0002-0497-721X"},"institutions":[{"id":"https://openalex.org/I83205935","display_name":"Malaviya National Institute of Technology Jaipur","ror":"https://ror.org/0077k1j32","country_code":"IN","type":"education","lineage":["https://openalex.org/I83205935"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"M. S. Gaur","raw_affiliation_strings":["MNIT, Jaipur, India"],"affiliations":[{"raw_affiliation_string":"MNIT, Jaipur, India","institution_ids":["https://openalex.org/I83205935"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014748272","display_name":"Megha Bhargava","orcid":null},"institutions":[{"id":"https://openalex.org/I99552915","display_name":"University of Rajasthan","ror":"https://ror.org/05arfhc56","country_code":"IN","type":"education","lineage":["https://openalex.org/I99552915"]},{"id":"https://openalex.org/I83205935","display_name":"Malaviya National Institute of Technology Jaipur","ror":"https://ror.org/0077k1j32","country_code":"IN","type":"education","lineage":["https://openalex.org/I83205935"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Megha Bhargava","raw_affiliation_strings":["MNIT, Jaipur, India","CCT, University of Rajasthan, Jaipur, India"],"affiliations":[{"raw_affiliation_string":"MNIT, Jaipur, India","institution_ids":["https://openalex.org/I83205935"]},{"raw_affiliation_string":"CCT, University of Rajasthan, Jaipur, India","institution_ids":["https://openalex.org/I99552915"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5054487156"],"corresponding_institution_ids":["https://openalex.org/I83205935"],"apc_list":null,"apc_paid":null,"fwci":0.3328,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.62898981,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mesi-protocol","display_name":"MESI protocol","score":0.8057465553283691},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7740062475204468},{"id":"https://openalex.org/keywords/directory","display_name":"Directory","score":0.759772539138794},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.7006644010543823},{"id":"https://openalex.org/keywords/mesif-protocol","display_name":"MESIF protocol","score":0.6545472145080566},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6179312467575073},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5616938471794128},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5499930381774902},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.49055975675582886},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4316827058792114},{"id":"https://openalex.org/keywords/protocol","display_name":"Protocol (science)","score":0.41839033365249634},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4125780165195465},{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.412563681602478},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3998384475708008},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3892943859100342},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.35867658257484436},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.29704803228378296},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.29168105125427246},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.27143746614456177}],"concepts":[{"id":"https://openalex.org/C120936851","wikidata":"https://www.wikidata.org/wiki/Q1408065","display_name":"MESI protocol","level":5,"score":0.8057465553283691},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7740062475204468},{"id":"https://openalex.org/C2777683733","wikidata":"https://www.wikidata.org/wiki/Q201456","display_name":"Directory","level":2,"score":0.759772539138794},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.7006644010543823},{"id":"https://openalex.org/C199979278","wikidata":"https://www.wikidata.org/wiki/Q263221","display_name":"MESIF protocol","level":5,"score":0.6545472145080566},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6179312467575073},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5616938471794128},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5499930381774902},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.49055975675582886},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4316827058792114},{"id":"https://openalex.org/C2780385302","wikidata":"https://www.wikidata.org/wiki/Q367158","display_name":"Protocol (science)","level":3,"score":0.41839033365249634},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4125780165195465},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.412563681602478},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3998384475708008},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3892943859100342},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.35867658257484436},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.29704803228378296},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.29168105125427246},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.27143746614456177},{"id":"https://openalex.org/C204787440","wikidata":"https://www.wikidata.org/wiki/Q188504","display_name":"Alternative medicine","level":2,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C142724271","wikidata":"https://www.wikidata.org/wiki/Q7208","display_name":"Pathology","level":1,"score":0.0},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvdat.2015.7208068","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2015.7208068","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 19th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6200000047683716,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2020018359","https://openalex.org/W2138598277","https://openalex.org/W2147657366","https://openalex.org/W2156126318","https://openalex.org/W2157225945","https://openalex.org/W4211192409","https://openalex.org/W6682565825"],"related_works":["https://openalex.org/W2290195868","https://openalex.org/W4285204597","https://openalex.org/W2584505417","https://openalex.org/W2140673013","https://openalex.org/W3193874149","https://openalex.org/W1555453305","https://openalex.org/W2987765027","https://openalex.org/W2352722396","https://openalex.org/W2155112318","https://openalex.org/W1499406481"],"abstract_inverted_index":{"Throughput-sensitive":[0],"server":[1],"workloads":[2],"are":[3],"expected":[4],"to":[5,49,70],"handle":[6],"voluminous":[7],"independent":[8],"and":[9,31],"concurrent":[10,37,54],"transactions":[11],"that":[12],"require":[13],"careful":[14],"designing":[15],"of":[16,22,53],"an":[17],"on":[18,46,67],"chip":[19,47,68],"interconnect.":[20],"State":[21],"the":[23,51],"art":[24],"applications":[25],"take":[26],"in":[27],"a":[28,62],"very":[29],"high":[30],"even":[32],"unbounded":[33],"working":[34],"sets":[35],"with":[36],"data.":[38],"It":[39],"demands":[40],"for":[41,45,74],"suitable":[42],"architectural":[43],"changes":[44],"interconnect":[48,69],"maintain":[50],"performance":[52],"applications.":[55],"In":[56],"this":[57],"paper,":[58],"we":[59],"have":[60],"proposed":[61],"novel":[63],"dual":[64],"link":[65],"mesh":[66],"classify":[71],"cache":[72,75],"traffic":[73],"coherence":[76],"MESI":[77],"directory":[78],"protocol.":[79]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}