{"id":"https://openalex.org/W2041144677","doi":"https://doi.org/10.1109/isvdat.2014.6881085","title":"A VLIW-Vector co-processor design for accelerating Basic Linear Algebraic Operations in OpenCV","display_name":"A VLIW-Vector co-processor design for accelerating Basic Linear Algebraic Operations in OpenCV","publication_year":2014,"publication_date":"2014-07-01","ids":{"openalex":"https://openalex.org/W2041144677","doi":"https://doi.org/10.1109/isvdat.2014.6881085","mag":"2041144677"},"language":"en","primary_location":{"id":"doi:10.1109/isvdat.2014.6881085","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2014.6881085","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"18th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5017099697","display_name":"Venkata Ganapathi Puppala","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Venkata Ganapathi Puppala","raw_affiliation_strings":["QLogic India Pvt Ltd, India","QLogic India Pvt Ltd., India"],"affiliations":[{"raw_affiliation_string":"QLogic India Pvt Ltd, India","institution_ids":[]},{"raw_affiliation_string":"QLogic India Pvt Ltd., India","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5017099697"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.9194,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.75084265,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"29","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-long-instruction-word","display_name":"Very long instruction word","score":0.8433831930160522},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8276154398918152},{"id":"https://openalex.org/keywords/porting","display_name":"Porting","score":0.6367151737213135},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.5565184354782104},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.5413155555725098},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5337335467338562},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5149510502815247},{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.5086241960525513},{"id":"https://openalex.org/keywords/floating-point","display_name":"Floating point","score":0.5011687278747559},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.44544780254364014},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.4338240623474121},{"id":"https://openalex.org/keywords/coprocessor","display_name":"Coprocessor","score":0.42824018001556396},{"id":"https://openalex.org/keywords/vector-processor","display_name":"Vector processor","score":0.42751598358154297},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.39151114225387573},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36480432748794556},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.15048006176948547},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.12731677293777466},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09436348080635071}],"concepts":[{"id":"https://openalex.org/C170595534","wikidata":"https://www.wikidata.org/wiki/Q249743","display_name":"Very long instruction word","level":2,"score":0.8433831930160522},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8276154398918152},{"id":"https://openalex.org/C106251023","wikidata":"https://www.wikidata.org/wiki/Q851989","display_name":"Porting","level":3,"score":0.6367151737213135},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.5565184354782104},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.5413155555725098},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5337335467338562},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5149510502815247},{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.5086241960525513},{"id":"https://openalex.org/C84211073","wikidata":"https://www.wikidata.org/wiki/Q117879","display_name":"Floating point","level":2,"score":0.5011687278747559},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.44544780254364014},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.4338240623474121},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.42824018001556396},{"id":"https://openalex.org/C161824985","wikidata":"https://www.wikidata.org/wiki/Q919509","display_name":"Vector processor","level":2,"score":0.42751598358154297},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.39151114225387573},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36480432748794556},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.15048006176948547},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.12731677293777466},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09436348080635071}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvdat.2014.6881085","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2014.6881085","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"18th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2020828929","https://openalex.org/W2119778797","https://openalex.org/W2132367502","https://openalex.org/W2141840788","https://openalex.org/W2545221752","https://openalex.org/W3004531124","https://openalex.org/W3157685993","https://openalex.org/W6729232845"],"related_works":["https://openalex.org/W2011126872","https://openalex.org/W2139795029","https://openalex.org/W1973931517","https://openalex.org/W2099279072","https://openalex.org/W4243317220","https://openalex.org/W4250324997","https://openalex.org/W2164026451","https://openalex.org/W2543652041","https://openalex.org/W1833231962","https://openalex.org/W2518412471"],"abstract_inverted_index":{"OpenCV":[0,25],"is":[1,112,119,133,151,172],"a":[2,45,57,70,92],"widely":[3],"used":[4],"computer":[5,30],"vision":[6,31],"library":[7],"written":[8],"in":[9,28,165],"C++.":[10],"Basic":[11],"Linear":[12],"Algebraic":[13],"Operations":[14],"(BLAOP)":[15],"involving":[16],"matrices":[17],"are":[18,141],"at":[19,85],"the":[20,29,42,50,106,138,144,154,158,176,184,187],"heart":[21],"of":[22,80,96],"OpenCV.":[23],"Though":[24],"provides":[26],"ubiquity":[27],"field,":[32],"it":[33,118],"runs":[34],"slow":[35],"when":[36,83],"ported":[37,173],"on":[38],"embedded":[39],"processors.":[40],"Accelerating":[41],"LAOPs":[43],"using":[44,114,121],"co-processor":[46,155],"certainly":[47],"helps":[48],"improving":[49],"throughput.":[51],"In":[52],"this":[53,199],"paper":[54],"we":[55],"present":[56],"floating":[58],"point":[59],"VLIW-Vector":[60],"Co-processor":[61],"Architecture":[62],"with":[63,125,153,186,198],"Vector":[64],"Floating":[65],"Point":[66],"Datapath":[67],"(VFPDP)":[68],"and":[69,117,137,163,183],"4-slot":[71],"VLIW":[72],"processor":[73,162,180],"core":[74],"to":[75,135,157],"accelerate":[76],"BLAOps":[77],"achieving":[78],"performance":[79,195],"two":[81],"GFLOPS":[82],"run":[84],"500MHz":[86],"clock":[87,131],"frequency.":[88],"We":[89],"also":[90],"demonstrate":[91],"detailed":[93],"mapping":[94],"strategy":[95],"One":[97],"sided":[98],"Jacobi":[99],"Singular":[100],"Value":[101],"Decomposition":[102],"(OJSVD)":[103],"algorithm":[104,171],"onto":[105,174],"proposed":[107,110,188],"architecture.":[108],"The":[109,130,169,190],"architecture":[111],"designed":[113],"Verilog":[115],"HDL":[116],"synthesized":[120],"Synopsis":[122],"Design":[123],"Compiler":[124],"28nm":[126],"TSMC":[127],"target":[128],"libraries.":[129],"period":[132],"set":[134],"2ns":[136],"timing":[139],"constraints":[140],"met.":[142],"Using":[143],"Altera's":[145],"SOPC":[146],"builder,":[147],"an":[148],"experimental":[149],"system":[150,182,185],"created":[152],"interfaced":[156],"NIOS":[159,178],"II":[160,179],"soft":[161],"implemented":[164],"Cyclone":[166],"IV":[167],"FPGA.":[168],"OJSVD":[170],"both":[175],"standalone":[177],"based":[181],"co-processor.":[189,200],"results":[191],"show":[192],"that":[193],"15X":[194],"improvement":[196],"achieved":[197]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}