{"id":"https://openalex.org/W2029162371","doi":"https://doi.org/10.1109/isvdat.2014.6881042","title":"Tunnel FET based low voltage static vs dynamic logic families for energy efficiency","display_name":"Tunnel FET based low voltage static vs dynamic logic families for energy efficiency","publication_year":2014,"publication_date":"2014-07-01","ids":{"openalex":"https://openalex.org/W2029162371","doi":"https://doi.org/10.1109/isvdat.2014.6881042","mag":"2029162371"},"language":"en","primary_location":{"id":"doi:10.1109/isvdat.2014.6881042","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2014.6881042","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"18th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079851995","display_name":"Kasturi Subramanyam","orcid":null},"institutions":[{"id":"https://openalex.org/I149313025","display_name":"Vignan's Foundation for Science, Technology & Research","ror":"https://ror.org/03bzf1g85","country_code":"IN","type":"education","lineage":["https://openalex.org/I149313025"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Kasturi Subramanyam","raw_affiliation_strings":["Electronics and Communication Engineering Department, VFSTR University, Guntur, AP, India","Electron. & Commun. Eng. Dept., VFSTR Univ., Guntur, India"],"affiliations":[{"raw_affiliation_string":"Electronics and Communication Engineering Department, VFSTR University, Guntur, AP, India","institution_ids":[]},{"raw_affiliation_string":"Electron. & Commun. Eng. Dept., VFSTR Univ., Guntur, India","institution_ids":["https://openalex.org/I149313025"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065565918","display_name":"Sadulla Shaik","orcid":"https://orcid.org/0000-0003-3119-8905"},"institutions":[{"id":"https://openalex.org/I149313025","display_name":"Vignan's Foundation for Science, Technology & Research","ror":"https://ror.org/03bzf1g85","country_code":"IN","type":"education","lineage":["https://openalex.org/I149313025"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sadulla Shaik","raw_affiliation_strings":["Electronics and Communication EnginegrinQad Department, VFSTR University, Guntur, AP, India","Electron. & Commun. Eng. Dept., VFSTR Univ., Guntur, India"],"affiliations":[{"raw_affiliation_string":"Electronics and Communication EnginegrinQad Department, VFSTR University, Guntur, AP, India","institution_ids":[]},{"raw_affiliation_string":"Electron. & Commun. Eng. Dept., VFSTR Univ., Guntur, India","institution_ids":["https://openalex.org/I149313025"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5086107411","display_name":"Ramesh Vaddi","orcid":"https://orcid.org/0000-0003-3158-4013"},"institutions":[{"id":"https://openalex.org/I26604189","display_name":"Shiv Nadar University","ror":"https://ror.org/05aqahr97","country_code":"IN","type":"education","lineage":["https://openalex.org/I26604189"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Ramesh Vaddi","raw_affiliation_strings":["Department of Electrical Engineering, Shiv Nadar University, Dadri, India","Dept. of Electr. Eng., Shiv Nadar Univ., Dadri, India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Shiv Nadar University, Dadri, India","institution_ids":["https://openalex.org/I26604189"]},{"raw_affiliation_string":"Dept. of Electr. Eng., Shiv Nadar Univ., Dadri, India","institution_ids":["https://openalex.org/I26604189"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5079851995"],"corresponding_institution_ids":["https://openalex.org/I149313025"],"apc_list":null,"apc_paid":null,"fwci":1.256,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.82306741,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.8436955213546753},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.7697958946228027},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.7141693830490112},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6783138513565063},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6041911840438843},{"id":"https://openalex.org/keywords/and-gate","display_name":"AND gate","score":0.49259501695632935},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4780997931957245},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4755958020687103},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.47202032804489136},{"id":"https://openalex.org/keywords/nor-gate","display_name":"NOR gate","score":0.46403810381889343},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.46203094720840454},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.45398157835006714},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.45391184091567993},{"id":"https://openalex.org/keywords/energy","display_name":"Energy (signal processing)","score":0.4446662664413452},{"id":"https://openalex.org/keywords/dynamic-logic","display_name":"Dynamic logic (digital electronics)","score":0.4381495714187622},{"id":"https://openalex.org/keywords/nand-logic","display_name":"NAND logic","score":0.416568785905838},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.4107668995857239},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.34654930233955383},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.27860283851623535},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.2002848982810974}],"concepts":[{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.8436955213546753},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.7697958946228027},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.7141693830490112},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6783138513565063},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6041911840438843},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.49259501695632935},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4780997931957245},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4755958020687103},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.47202032804489136},{"id":"https://openalex.org/C126445297","wikidata":"https://www.wikidata.org/wiki/Q8065380","display_name":"NOR gate","level":4,"score":0.46403810381889343},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.46203094720840454},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.45398157835006714},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.45391184091567993},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.4446662664413452},{"id":"https://openalex.org/C2777796570","wikidata":"https://www.wikidata.org/wiki/Q2351326","display_name":"Dynamic logic (digital electronics)","level":4,"score":0.4381495714187622},{"id":"https://openalex.org/C7234692","wikidata":"https://www.wikidata.org/wiki/Q4116068","display_name":"NAND logic","level":4,"score":0.416568785905838},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.4107668995857239},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.34654930233955383},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.27860283851623535},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.2002848982810974},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvdat.2014.6881042","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvdat.2014.6881042","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"18th International Symposium on VLSI Design and Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.9100000262260437}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2050005714","https://openalex.org/W2115224472"],"related_works":["https://openalex.org/W188762367","https://openalex.org/W4361799621","https://openalex.org/W1017999001","https://openalex.org/W2765195743","https://openalex.org/W2616524835","https://openalex.org/W2024713617","https://openalex.org/W24644591","https://openalex.org/W2791832526","https://openalex.org/W2917652992","https://openalex.org/W2592373406"],"abstract_inverted_index":{"Tunnel":[0,24],"FETs":[1],"as":[2],"steep":[3,56,123],"slope":[4,57],"devices":[5],"have":[6,61],"attracted":[7],"attention":[8],"for":[9,30,36],"achieving":[10],"energy":[11,63,86,118,140,150],"efficiency":[12,64,119],"at":[13,157],"low":[14,125],"supply":[15,50],"voltages.":[16],"This":[17],"paper":[18],"presents":[19],"the":[20,37,55,96],"design":[21],"of":[22,95,117],"Hetero-junction":[23],"FET":[25],"(HTFET)":[26],"based":[27],"logic":[28,34,78,92,106,135],"gates":[29,107,111],"static":[31,77,91,110,126,144],"and":[32,112,128,147],"dynamic":[33,105,134,154],"topologies":[35,60],"first":[38],"time.":[39],"Comparison":[40],"is":[41,83,102],"also":[42],"done":[43],"with":[44,49],"20nm":[45],"Si":[46,68,89],"FinFET":[47,69,90,113,153],"technology":[48],"voltage":[51],"scaling.":[52],"Due":[53],"to":[54,67,121],"characteristics,":[58],"HTFET":[59,76,104,109,133,143],"improved":[62],"in":[65,115],"comparison":[66],"configurations.":[70],"It":[71],"has":[72,137],"been":[73],"observed":[74],"that":[75,103],"gate":[79,136,146,156],"(two":[80],"input":[81],"NAND)":[82],"~60%":[84],"more":[85],"efficient":[87],"then":[88],"gate.":[93],"One":[94],"key":[97],"findings":[98],"from":[99],"this":[100],"work":[101],"outperform":[108],"designs":[114],"terms":[116],"due":[120],"HTFET's":[122],"slope,":[124],"power":[127],"reduced":[129],"delay":[130],"values.":[131],"The":[132],"~65%":[138],"less":[139,149],"consumption":[141,151],"than":[142,152],"NAND":[145,155],"~56%":[148],"V":[158],"<inf":[159],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[160],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">dd</inf>":[161],"=0.2V.":[162]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}