{"id":"https://openalex.org/W2031068066","doi":"https://doi.org/10.1109/isscc.2008.4523230","title":"An All-Digital On-Chip Process-Control Monitor for Process-Variability Measurements","display_name":"An All-Digital On-Chip Process-Control Monitor for Process-Variability Measurements","publication_year":2008,"publication_date":"2008-02-01","ids":{"openalex":"https://openalex.org/W2031068066","doi":"https://doi.org/10.1109/isscc.2008.4523230","mag":"2031068066"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2008.4523230","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2008.4523230","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021465692","display_name":"F. Klass","orcid":null},"institutions":[{"id":"https://openalex.org/I16269868","display_name":"Santa Clara University","ror":"https://ror.org/03ypqe447","country_code":"US","type":"education","lineage":["https://openalex.org/I16269868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fabian Klass","raw_affiliation_strings":["Santa Clara, CA, USA","P. A. Semi, Santa Clara, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Santa Clara, CA, USA","institution_ids":["https://openalex.org/I16269868"]},{"raw_affiliation_string":"P. A. Semi, Santa Clara, CA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076142639","display_name":"Ashish Jain","orcid":"https://orcid.org/0000-0001-6549-1734"},"institutions":[{"id":"https://openalex.org/I16269868","display_name":"Santa Clara University","ror":"https://ror.org/03ypqe447","country_code":"US","type":"education","lineage":["https://openalex.org/I16269868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ashish Jain","raw_affiliation_strings":["Santa Clara, CA, USA","P. A. Semi, Santa Clara, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Santa Clara, CA, USA","institution_ids":["https://openalex.org/I16269868"]},{"raw_affiliation_string":"P. A. Semi, Santa Clara, CA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044167263","display_name":"Greg Hess","orcid":null},"institutions":[{"id":"https://openalex.org/I16269868","display_name":"Santa Clara University","ror":"https://ror.org/03ypqe447","country_code":"US","type":"education","lineage":["https://openalex.org/I16269868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Greg Hess","raw_affiliation_strings":["Santa Clara, CA, USA","P. A. Semi, Santa Clara, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Santa Clara, CA, USA","institution_ids":["https://openalex.org/I16269868"]},{"raw_affiliation_string":"P. A. Semi, Santa Clara, CA","institution_ids":[]}]},{"author_position":"last","author":{"id":null,"display_name":"Brian Park","orcid":null},"institutions":[{"id":"https://openalex.org/I16269868","display_name":"Santa Clara University","ror":"https://ror.org/03ypqe447","country_code":"US","type":"education","lineage":["https://openalex.org/I16269868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Brian Park","raw_affiliation_strings":["Santa Clara, CA, USA","P. A. Semi, Santa Clara, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Santa Clara, CA, USA","institution_ids":["https://openalex.org/I16269868"]},{"raw_affiliation_string":"P. A. Semi, Santa Clara, CA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.1439,"has_fulltext":false,"cited_by_count":23,"citation_normalized_percentile":{"value":0.94175417,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"408","last_page":"623"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.8916000127792358,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.8916000127792358,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.8136000037193298,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.8015999794006348,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.653904914855957},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5935009121894836},{"id":"https://openalex.org/keywords/process-control","display_name":"Process control","score":0.5927911400794983},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4732827842235565},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.418832927942276},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3529598116874695},{"id":"https://openalex.org/keywords/process-engineering","display_name":"Process engineering","score":0.33453744649887085},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1558707058429718},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.14360931515693665},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07600376009941101}],"concepts":[{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.653904914855957},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5935009121894836},{"id":"https://openalex.org/C155386361","wikidata":"https://www.wikidata.org/wiki/Q1649571","display_name":"Process control","level":3,"score":0.5927911400794983},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4732827842235565},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.418832927942276},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3529598116874695},{"id":"https://openalex.org/C21880701","wikidata":"https://www.wikidata.org/wiki/Q2144042","display_name":"Process engineering","level":1,"score":0.33453744649887085},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1558707058429718},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.14360931515693665},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07600376009941101}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2008.4523230","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2008.4523230","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5799999833106995}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2042809000","https://openalex.org/W2061953318","https://openalex.org/W2079706534","https://openalex.org/W2140823559","https://openalex.org/W6665870340"],"related_works":["https://openalex.org/W2036806516","https://openalex.org/W2065289416","https://openalex.org/W1967394420","https://openalex.org/W2565425548","https://openalex.org/W2392009442","https://openalex.org/W2087695844","https://openalex.org/W2017236304","https://openalex.org/W2154106283","https://openalex.org/W2912613323","https://openalex.org/W2142443274"],"abstract_inverted_index":{"Process":[0],"variability":[1,12,33],"has":[2],"become":[3],"a":[4,15],"major":[5],"challenge":[6],"in":[7],"nanometer":[8],"technologies.":[9],"Understanding":[10],"process":[11,27,32],"is":[13,34],"therefore":[14],"key":[16],"to":[17],"designing":[18],"successful":[19],"low-power":[20],"multi-million":[21],"gate":[22],"SoCs.":[23],"An":[24],"all-digital":[25],"on-chip":[26],"control-monitor":[28],"(PCM)":[29],"that":[30],"measures":[31],"described.":[35]},"counts_by_year":[{"year":2022,"cited_by_count":3},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}