{"id":"https://openalex.org/W2023181070","doi":"https://doi.org/10.1109/isqed.2012.6187579","title":"Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis","display_name":"Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis","publication_year":2012,"publication_date":"2012-03-01","ids":{"openalex":"https://openalex.org/W2023181070","doi":"https://doi.org/10.1109/isqed.2012.6187579","mag":"2023181070"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2012.6187579","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2012.6187579","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102119602","display_name":"Keisuke Inoue","orcid":null},"institutions":[{"id":"https://openalex.org/I177738480","display_name":"Japan Advanced Institute of Science and Technology","ror":"https://ror.org/03frj4r98","country_code":"JP","type":"education","lineage":["https://openalex.org/I177738480"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Keisuke Inoue","raw_affiliation_strings":["School of Information Science, Japan Advanced Institute of Science and Technology, Nomi, Ishikawa, Japan","School of Information Science, Japan Advanced Institute of Science and Technology (JAIST), 1-1, Asahidai, Nomi-shi, Ishikawa 923-1292 JAPAN"],"affiliations":[{"raw_affiliation_string":"School of Information Science, Japan Advanced Institute of Science and Technology, Nomi, Ishikawa, Japan","institution_ids":["https://openalex.org/I177738480"]},{"raw_affiliation_string":"School of Information Science, Japan Advanced Institute of Science and Technology (JAIST), 1-1, Asahidai, Nomi-shi, Ishikawa 923-1292 JAPAN","institution_ids":["https://openalex.org/I177738480"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112420841","display_name":"Mineo Kaneko","orcid":null},"institutions":[{"id":"https://openalex.org/I177738480","display_name":"Japan Advanced Institute of Science and Technology","ror":"https://ror.org/03frj4r98","country_code":"JP","type":"education","lineage":["https://openalex.org/I177738480"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Mineo Kaneko","raw_affiliation_strings":["School of Information Science, Japan Advanced Institute of Science and Technology, Nomi, Ishikawa, Japan","School of Information Science, Japan Advanced Institute of Science and Technology (JAIST), 1-1, Asahidai, Nomi-shi, Ishikawa 923-1292 JAPAN"],"affiliations":[{"raw_affiliation_string":"School of Information Science, Japan Advanced Institute of Science and Technology, Nomi, Ishikawa, Japan","institution_ids":["https://openalex.org/I177738480"]},{"raw_affiliation_string":"School of Information Science, Japan Advanced Institute of Science and Technology (JAIST), 1-1, Asahidai, Nomi-shi, Ishikawa 923-1292 JAPAN","institution_ids":["https://openalex.org/I177738480"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5102119602"],"corresponding_institution_ids":["https://openalex.org/I177738480"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.09359191,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"e84 a","issue":null,"first_page":"778","last_page":"783"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.8916445970535278},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.8089537024497986},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7699700593948364},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6913514733314514},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.676713764667511},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.6123531460762024},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.5963369607925415},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5633791089057922},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.5520124435424805},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5142762064933777},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.509722888469696},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.45612847805023193},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.42868298292160034},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3879380226135254},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3176945447921753},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2800707221031189},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.17078712582588196},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.16997304558753967},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.15445995330810547},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.10004845261573792},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08902248740196228}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.8916445970535278},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.8089537024497986},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7699700593948364},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6913514733314514},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.676713764667511},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.6123531460762024},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.5963369607925415},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5633791089057922},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.5520124435424805},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5142762064933777},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.509722888469696},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.45612847805023193},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.42868298292160034},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3879380226135254},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3176945447921753},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2800707221031189},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.17078712582588196},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.16997304558753967},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.15445995330810547},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.10004845261573792},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08902248740196228},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2012.6187579","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2012.6187579","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":36,"referenced_works":["https://openalex.org/W582146233","https://openalex.org/W1530705060","https://openalex.org/W1930768720","https://openalex.org/W1977545325","https://openalex.org/W1988123824","https://openalex.org/W2000655923","https://openalex.org/W2011778848","https://openalex.org/W2076907308","https://openalex.org/W2093660707","https://openalex.org/W2096283348","https://openalex.org/W2100928338","https://openalex.org/W2103770709","https://openalex.org/W2107369146","https://openalex.org/W2113367047","https://openalex.org/W2114266730","https://openalex.org/W2129183345","https://openalex.org/W2135347849","https://openalex.org/W2150660745","https://openalex.org/W2150749964","https://openalex.org/W2154150759","https://openalex.org/W2163318442","https://openalex.org/W2164363818","https://openalex.org/W2164431584","https://openalex.org/W2174922170","https://openalex.org/W3004540582","https://openalex.org/W3141997571","https://openalex.org/W3145128584","https://openalex.org/W3146131994","https://openalex.org/W3149293211","https://openalex.org/W4213060235","https://openalex.org/W4231706861","https://openalex.org/W4236186638","https://openalex.org/W4247089581","https://openalex.org/W4255150597","https://openalex.org/W6631680385","https://openalex.org/W6650546730"],"related_works":["https://openalex.org/W4247089581","https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W1662010573","https://openalex.org/W1938797020","https://openalex.org/W60672686","https://openalex.org/W2174922170","https://openalex.org/W2040807843","https://openalex.org/W2090556728","https://openalex.org/W2117863281"],"abstract_inverted_index":{"Nowadays,":[0],"clock":[1,14,31,47],"skew":[2,48],"becomes":[3,33],"a":[4,12,26,36,82],"manageable":[5],"resource":[6],"to":[7,16,98],"improve":[8],"circuits":[9,118],"by":[10],"assigning":[11],"certain":[13],"delay":[15],"each":[17],"register.":[18],"However,":[19],"it":[20],"has":[21,51],"been":[22,52],"reported":[23],"that":[24,75],"implementing":[25],"large":[27],"spectrum":[28],"of":[29,68,88,122],"dedicated":[30],"delays":[32],"challenging":[34],"in":[35,56,111],"reliable":[37],"manner":[38],"under":[39],"several":[40,116],"uncertainties.":[41],"To":[42],"overcome":[43],"this":[44],"limitation,":[45],"multi-domain":[46],"scheduling":[49],"(MDCSS)":[50],"proposed,":[53],"and":[54,58,73,78],"studied":[55],"logic-":[57],"physical-level":[59],"design":[60],"stages.":[61],"This":[62],"paper":[63],"firstly":[64],"introduce":[65],"the":[66,86,89,120,123],"concept":[67],"MDCSS":[69],"into":[70],"high-level":[71],"synthesis,":[72],"shows":[74],"register":[76],"binding":[77],"domain":[79],"assignment":[80],"have":[81],"significant":[83],"impact":[84],"on":[85,115],"performance":[87],"resulting":[90],"datapath.":[91],"A":[92],"mixed":[93],"integer":[94],"linear":[95],"program":[96],"model":[97],"optimize":[99],"MDCSS-based":[100,112],"datapath":[101],"is":[102],"presented,":[103],"which":[104],"can":[105],"be":[106],"used":[107],"for":[108],"various":[109],"objectives":[110],"design.":[113],"Experiments":[114],"benchmark":[117],"validate":[119],"effectiveness":[121],"approach.":[124]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
