{"id":"https://openalex.org/W1966127142","doi":"https://doi.org/10.1109/isqed.2012.6187549","title":"An accurate current source model for CMOS based combinational logic cell","display_name":"An accurate current source model for CMOS based combinational logic cell","publication_year":2012,"publication_date":"2012-03-01","ids":{"openalex":"https://openalex.org/W1966127142","doi":"https://doi.org/10.1109/isqed.2012.6187549","mag":"1966127142"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2012.6187549","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2012.6187549","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060678180","display_name":"Baljit Kaur","orcid":"https://orcid.org/0000-0002-4820-2336"},"institutions":[{"id":"https://openalex.org/I154851008","display_name":"Indian Institute of Technology Roorkee","ror":"https://ror.org/00582g326","country_code":"IN","type":"education","lineage":["https://openalex.org/I154851008"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Baljit Kaur","raw_affiliation_strings":["Department of Electronics & Computer Engineering, Indian Institute of Technology Roorkee, Roorkee, India","Department of Electronics and Computer Engineering; Indian Institute of Technology Roorkee; Roorkee India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics & Computer Engineering, Indian Institute of Technology Roorkee, Roorkee, India","institution_ids":["https://openalex.org/I154851008"]},{"raw_affiliation_string":"Department of Electronics and Computer Engineering; Indian Institute of Technology Roorkee; Roorkee India","institution_ids":["https://openalex.org/I154851008"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059026784","display_name":"Sandeep Vundavalli","orcid":null},"institutions":[{"id":"https://openalex.org/I154851008","display_name":"Indian Institute of Technology Roorkee","ror":"https://ror.org/00582g326","country_code":"IN","type":"education","lineage":["https://openalex.org/I154851008"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sandeep Vundavalli","raw_affiliation_strings":["Department of Electronics & Computer Engineering, Indian Institute of Technology Roorkee, Roorkee, India","Department of Electronics and Computer Engineering; Indian Institute of Technology Roorkee; Roorkee India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics & Computer Engineering, Indian Institute of Technology Roorkee, Roorkee, India","institution_ids":["https://openalex.org/I154851008"]},{"raw_affiliation_string":"Department of Electronics and Computer Engineering; Indian Institute of Technology Roorkee; Roorkee India","institution_ids":["https://openalex.org/I154851008"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059645325","display_name":"S. K. Manhas","orcid":"https://orcid.org/0000-0003-3360-9683"},"institutions":[{"id":"https://openalex.org/I154851008","display_name":"Indian Institute of Technology Roorkee","ror":"https://ror.org/00582g326","country_code":"IN","type":"education","lineage":["https://openalex.org/I154851008"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"S. K. Manhas","raw_affiliation_strings":["Department of Electronics & Computer Engineering, Indian Institute of Technology Roorkee, Roorkee, India","Department of Electronics and Computer Engineering; Indian Institute of Technology Roorkee; Roorkee India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics & Computer Engineering, Indian Institute of Technology Roorkee, Roorkee, India","institution_ids":["https://openalex.org/I154851008"]},{"raw_affiliation_string":"Department of Electronics and Computer Engineering; Indian Institute of Technology Roorkee; Roorkee India","institution_ids":["https://openalex.org/I154851008"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064560509","display_name":"Sudeb Dasgupta","orcid":"https://orcid.org/0000-0002-4044-1594"},"institutions":[{"id":"https://openalex.org/I154851008","display_name":"Indian Institute of Technology Roorkee","ror":"https://ror.org/00582g326","country_code":"IN","type":"education","lineage":["https://openalex.org/I154851008"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"S. Dasgupta","raw_affiliation_strings":["Department of Electronics & Computer Engineering, Indian Institute of Technology Roorkee, Roorkee, India","Department of Electronics and Computer Engineering; Indian Institute of Technology Roorkee; Roorkee India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics & Computer Engineering, Indian Institute of Technology Roorkee, Roorkee, India","institution_ids":["https://openalex.org/I154851008"]},{"raw_affiliation_string":"Department of Electronics and Computer Engineering; Indian Institute of Technology Roorkee; Roorkee India","institution_ids":["https://openalex.org/I154851008"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031850929","display_name":"Anand Bulusu","orcid":"https://orcid.org/0000-0002-3986-3730"},"institutions":[{"id":"https://openalex.org/I154851008","display_name":"Indian Institute of Technology Roorkee","ror":"https://ror.org/00582g326","country_code":"IN","type":"education","lineage":["https://openalex.org/I154851008"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Bulusu Anand","raw_affiliation_strings":["Department of Electronics & Computer Engineering, Indian Institute of Technology Roorkee, Roorkee, India","Department of Electronics and Computer Engineering; Indian Institute of Technology Roorkee; Roorkee India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics & Computer Engineering, Indian Institute of Technology Roorkee, Roorkee, India","institution_ids":["https://openalex.org/I154851008"]},{"raw_affiliation_string":"Department of Electronics and Computer Engineering; Indian Institute of Technology Roorkee; Roorkee India","institution_ids":["https://openalex.org/I154851008"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5060678180"],"corresponding_institution_ids":["https://openalex.org/I154851008"],"apc_list":null,"apc_paid":null,"fwci":0.7365,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.72400056,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"561","last_page":"565"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.8420200943946838},{"id":"https://openalex.org/keywords/waveform","display_name":"Waveform","score":0.8162165880203247},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.6799792647361755},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6564086079597473},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5542638301849365},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5491877794265747},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.5288540124893188},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4773671329021454},{"id":"https://openalex.org/keywords/semiconductor-device-modeling","display_name":"Semiconductor device modeling","score":0.45282161235809326},{"id":"https://openalex.org/keywords/integrated-injection-logic","display_name":"Integrated injection logic","score":0.4323035180568695},{"id":"https://openalex.org/keywords/current-source","display_name":"Current source","score":0.42096009850502014},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.37418821454048157},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.35309964418411255},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.34489864110946655},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.13611522316932678}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.8420200943946838},{"id":"https://openalex.org/C197424946","wikidata":"https://www.wikidata.org/wiki/Q1165717","display_name":"Waveform","level":3,"score":0.8162165880203247},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.6799792647361755},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6564086079597473},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5542638301849365},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5491877794265747},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.5288540124893188},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4773671329021454},{"id":"https://openalex.org/C4775677","wikidata":"https://www.wikidata.org/wiki/Q7449393","display_name":"Semiconductor device modeling","level":3,"score":0.45282161235809326},{"id":"https://openalex.org/C159903706","wikidata":"https://www.wikidata.org/wiki/Q173574","display_name":"Integrated injection logic","level":5,"score":0.4323035180568695},{"id":"https://openalex.org/C2781331714","wikidata":"https://www.wikidata.org/wiki/Q1163768","display_name":"Current source","level":3,"score":0.42096009850502014},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.37418821454048157},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.35309964418411255},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.34489864110946655},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.13611522316932678}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2012.6187549","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2012.6187549","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8299999833106995}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1547254974","https://openalex.org/W1562054836","https://openalex.org/W2034793671","https://openalex.org/W2053853976","https://openalex.org/W2104726505","https://openalex.org/W2105904555","https://openalex.org/W2108816571","https://openalex.org/W2114252285","https://openalex.org/W2128406327","https://openalex.org/W2133268384","https://openalex.org/W2145146339","https://openalex.org/W2155302120","https://openalex.org/W3145469858","https://openalex.org/W4231442584","https://openalex.org/W4237823089","https://openalex.org/W4255738297","https://openalex.org/W6659279280"],"related_works":["https://openalex.org/W1515819608","https://openalex.org/W1485027372","https://openalex.org/W3017501411","https://openalex.org/W1900707063","https://openalex.org/W2074526596","https://openalex.org/W2140909357","https://openalex.org/W4242010157","https://openalex.org/W2119623427","https://openalex.org/W1843096359","https://openalex.org/W1847737738"],"abstract_inverted_index":{"A":[0],"current":[1,25],"source":[2],"model":[3,28,35,48,83,102],"(CSM)":[4],"is":[5,64,84,103],"presented":[6],"for":[7,15,36,49,96,136],"CMOS":[8,21,50,78],"logic":[9,51,69],"cells,":[10],"which":[11],"can":[12,29],"be":[13,30],"used":[14],"accurate":[16,34,104],"analysis":[17],"of":[18,55,76,92,100,128,139],"delay":[19],"in":[20],"VLSI":[22],"circuits.":[23],"In":[24],"technology,":[26],"CS":[27,47,82,101,118],"considered":[31],"as":[32,71,105,107],"an":[33,93],"modern":[37],"static":[38],"timing":[39],"and":[40,141],"noise":[41],"analysis.":[42],"By":[43,115],"using":[44,81,116],"the":[45,68,77,111,117],"combinational":[46],"cell,":[52],"different":[53,120,137],"values":[54,138],"parasitic":[56,121,130],"capacitances":[57,122,131],"are":[58,123,132],"correctly":[59],"evaluated.":[60,126],"Output":[61],"voltage":[62,75,90,98],"waveform":[63,91,99],"designed":[65],"by":[66,80],"considering":[67],"cell":[70],"load.":[72],"The":[73],"output":[74,89,97,142],"inverter":[79],"compared":[85],"with":[86],"HSPICE":[87,112],"simulated":[88,113],"inverter.":[94],"Analysis":[95],"near":[106],"approximately":[108],"98%":[109],"to":[110],"waveform.":[114],"model,":[119],"also":[124,133],"being":[125,134],"Variations":[127],"these":[129],"evaluated":[135],"input":[140],"voltages.":[143]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
