{"id":"https://openalex.org/W2142408549","doi":"https://doi.org/10.1109/isqed.2009.4810365","title":"Efficient statistical analysis of read timing failures in SRAM circuits","display_name":"Efficient statistical analysis of read timing failures in SRAM circuits","publication_year":2009,"publication_date":"2009-03-01","ids":{"openalex":"https://openalex.org/W2142408549","doi":"https://doi.org/10.1109/isqed.2009.4810365","mag":"2142408549"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2009.4810365","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2009.4810365","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 10th International Symposium on Quality of Electronic Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055160439","display_name":"Soner Yaldiz","orcid":"https://orcid.org/0000-0002-0715-0859"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Soner Yaldiz","raw_affiliation_strings":["Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, USA","Electrical and Computer Engineering Department, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA 15213, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Electrical and Computer Engineering Department, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA 15213, USA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101505371","display_name":"\u00dcm\u00fct Arslan","orcid":"https://orcid.org/0000-0002-3611-9607"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Umut Arslan","raw_affiliation_strings":["Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, USA","Electrical and Computer Engineering Department, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA 15213, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Electrical and Computer Engineering Department, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA 15213, USA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100353869","display_name":"Xin Li","orcid":"https://orcid.org/0000-0002-4510-2436"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xin Li","raw_affiliation_strings":["Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, USA","Electrical and Computer Engineering Department, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA 15213, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Electrical and Computer Engineering Department, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA 15213, USA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033242808","display_name":"Larry Pileggi","orcid":"https://orcid.org/0000-0002-8605-8240"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Larry Pileggi","raw_affiliation_strings":["Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, USA","Electrical and Computer Engineering Department, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA 15213, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Electrical and Computer Engineering Department, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA 15213, USA","institution_ids":["https://openalex.org/I74973139"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5055160439"],"corresponding_institution_ids":["https://openalex.org/I74973139"],"apc_list":null,"apc_paid":null,"fwci":0.6096,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.73507205,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"617","last_page":"621"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.8953335285186768},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7086057662963867},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.6411998867988586},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.6073015928268433},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.5355724096298218},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5296691656112671},{"id":"https://openalex.org/keywords/bounding-overwatch","display_name":"Bounding overwatch","score":0.5131593346595764},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.48819977045059204},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.45203083753585815},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4445534646511078},{"id":"https://openalex.org/keywords/sense-amplifier","display_name":"Sense amplifier","score":0.41740623116493225},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3619966506958008},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3327358663082123},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2046087086200714},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1574961245059967},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.15564611554145813},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.12861594557762146},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11104550957679749},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1027059257030487},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.07564243674278259},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.07338830828666687}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.8953335285186768},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7086057662963867},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.6411998867988586},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.6073015928268433},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.5355724096298218},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5296691656112671},{"id":"https://openalex.org/C63584917","wikidata":"https://www.wikidata.org/wiki/Q333286","display_name":"Bounding overwatch","level":2,"score":0.5131593346595764},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.48819977045059204},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.45203083753585815},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4445534646511078},{"id":"https://openalex.org/C32666082","wikidata":"https://www.wikidata.org/wiki/Q7450979","display_name":"Sense amplifier","level":3,"score":0.41740623116493225},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3619966506958008},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3327358663082123},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2046087086200714},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1574961245059967},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.15564611554145813},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.12861594557762146},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11104550957679749},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1027059257030487},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.07564243674278259},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.07338830828666687},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/isqed.2009.4810365","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2009.4810365","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 10th International Symposium on Quality of Electronic Design","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.157.3965","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.157.3965","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.cmu.edu/~xinli/papers/2009_ISQED_sram.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2066274996","https://openalex.org/W2097399506","https://openalex.org/W2100483769","https://openalex.org/W2103793078","https://openalex.org/W2120353978","https://openalex.org/W2132621842","https://openalex.org/W2145345888","https://openalex.org/W2150220758","https://openalex.org/W3143794633","https://openalex.org/W3149402879","https://openalex.org/W3151457670","https://openalex.org/W6667144751","https://openalex.org/W6682013172"],"related_works":["https://openalex.org/W1835913819","https://openalex.org/W2548084981","https://openalex.org/W2051363901","https://openalex.org/W2127348582","https://openalex.org/W2136142653","https://openalex.org/W2373152541","https://openalex.org/W2174410816","https://openalex.org/W3209598999","https://openalex.org/W2159817233","https://openalex.org/W2107909712"],"abstract_inverted_index":{"A":[0],"system-level":[1,42],"statistical":[2],"analysis":[3],"methodology":[4,72,94],"is":[5,44,53,73],"described":[6],"that":[7,28,52],"captures":[8],"the":[9,41,48,90],"impact":[10],"of":[11,66,92,114],"inter-":[12],"and":[13,107],"intra-die":[14],"process":[15],"variations":[16],"for":[17,34,47,95],"read":[18,67],"timing":[19,68],"failures":[20,69],"in":[21,84],"SRAM":[22,50,82],"circuit":[23,51,109],"blocks.":[24],"Unlike":[25],"existing":[26],"approaches":[27],"focus":[29],"on":[30],"cell-level":[31],"performance":[32,43],"metrics":[33],"isolated":[35],"sub-components":[36],"or":[37],"ignore":[38],"inter-die":[39],"variability,":[40],"accurately":[45],"predicted":[46],"entire":[49],"impractical":[54],"to":[55,100],"analyze":[56],"statistically":[57],"via":[58],"transistor-level":[59],"Monte":[60],"Carlo":[61],"simulations.":[62],"The":[63],"accurate":[64],"bounding":[65],"using":[70],"this":[71,93],"validated":[74],"with":[75],"silicon":[76],"measurements":[77],"from":[78],"a":[79,112],"64":[80],"kb":[81],"testchip":[83],"90":[85],"nm":[86],"CMOS.":[87],"We":[88],"demonstrate":[89],"efficacy":[91],"early":[96],"stage":[97],"design":[98],"exploration":[99],"specify":[101],"redundancy,":[102],"required":[103],"sense":[104],"amp":[105],"offset,":[106],"other":[108],"choices":[110],"as":[111],"function":[113],"memory":[115],"size.":[116]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":2}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}