{"id":"https://openalex.org/W2098204276","doi":"https://doi.org/10.1109/isqed.2007.6","title":"A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits","display_name":"A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits","publication_year":2007,"publication_date":"2007-03-01","ids":{"openalex":"https://openalex.org/W2098204276","doi":"https://doi.org/10.1109/isqed.2007.6","mag":"2098204276"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2007.6","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2007.6","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"8th International Symposium on Quality Electronic Design (ISQED'07)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074746150","display_name":"Vyas Krishnan","orcid":null},"institutions":[{"id":"https://openalex.org/I2613432","display_name":"University of South Florida","ror":"https://ror.org/032db5x82","country_code":"US","type":"education","lineage":["https://openalex.org/I2613432"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Vyas Krishnan","raw_affiliation_strings":["Department of Computer Science and Engineering, University of South Florida, Tampa, FL, USA","Dept. of Comput. Sci. & Eng., South Florida Univ., Tampa, FL"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, University of South Florida, Tampa, FL, USA","institution_ids":["https://openalex.org/I2613432"]},{"raw_affiliation_string":"Dept. of Comput. Sci. & Eng., South Florida Univ., Tampa, FL","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5016167446","display_name":"Srinivas Katkoori","orcid":"https://orcid.org/0000-0002-7589-5836"},"institutions":[{"id":"https://openalex.org/I2613432","display_name":"University of South Florida","ror":"https://ror.org/032db5x82","country_code":"US","type":"education","lineage":["https://openalex.org/I2613432"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Srinivas Katkoori","raw_affiliation_strings":["Department of Computer Science and Engineering, University of South Florida, Tampa, FL, USA","Dept. of Comput. Sci. & Eng., South Florida Univ., Tampa, FL"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, University of South Florida, Tampa, FL, USA","institution_ids":["https://openalex.org/I2613432"]},{"raw_affiliation_string":"Dept. of Comput. Sci. & Eng., South Florida Univ., Tampa, FL","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5074746150"],"corresponding_institution_ids":["https://openalex.org/I2613432"],"apc_list":null,"apc_paid":null,"fwci":2.1529,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.87761139,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"885","last_page":"892"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.8351391553878784},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.7125591039657593},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.6837993860244751},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6776456832885742},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.5959165096282959},{"id":"https://openalex.org/keywords/ic-layout-editor","display_name":"IC layout editor","score":0.5550435781478882},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5044859647750854},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.47504544258117676},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.45791593194007874},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.45388326048851013},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.4535572826862335},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.45089060068130493},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.44237300753593445},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.43076950311660767},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4218767285346985},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.38545554876327515},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.353748619556427},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.3016030490398407},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2877156734466553},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.19757810235023499},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17779803276062012},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.16481226682662964},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.11545827984809875},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09610432386398315}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.8351391553878784},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.7125591039657593},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.6837993860244751},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6776456832885742},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.5959165096282959},{"id":"https://openalex.org/C5546195","wikidata":"https://www.wikidata.org/wiki/Q5969842","display_name":"IC layout editor","level":5,"score":0.5550435781478882},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5044859647750854},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.47504544258117676},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.45791593194007874},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.45388326048851013},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.4535572826862335},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.45089060068130493},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.44237300753593445},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.43076950311660767},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4218767285346985},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.38545554876327515},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.353748619556427},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.3016030490398407},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2877156734466553},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.19757810235023499},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17779803276062012},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.16481226682662964},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.11545827984809875},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09610432386398315},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2007.6","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2007.6","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"8th International Symposium on Quality Electronic Design (ISQED'07)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1506241038","https://openalex.org/W2009083496","https://openalex.org/W2027918523","https://openalex.org/W2072400712","https://openalex.org/W2074601596","https://openalex.org/W2097099414","https://openalex.org/W2101987243","https://openalex.org/W2105076302","https://openalex.org/W2113911387","https://openalex.org/W2121318787","https://openalex.org/W2125653639","https://openalex.org/W2137893918","https://openalex.org/W2154462472","https://openalex.org/W2154907195","https://openalex.org/W2170295440","https://openalex.org/W2626746498","https://openalex.org/W4248717925","https://openalex.org/W4255374779","https://openalex.org/W6652498935","https://openalex.org/W6675804706"],"related_works":["https://openalex.org/W2091329789","https://openalex.org/W2376726667","https://openalex.org/W162881505","https://openalex.org/W2150722449","https://openalex.org/W4238891425","https://openalex.org/W2357425846","https://openalex.org/W2125213949","https://openalex.org/W1605062719","https://openalex.org/W2376028644","https://openalex.org/W1965232212"],"abstract_inverted_index":{"Recent":[0],"progress":[1],"in":[2,28,55,186],"the":[3,12,46,60,84,102,127,150,154,162,169],"fabrication":[4],"of":[5,14,48,51,70,105,109,171],"three-dimensional":[6,34,65],"integrated":[7,35,42,66],"circuits":[8,43,72],"has":[9],"opened":[10],"up":[11],"possibility":[13],"exploiting":[15],"this":[16],"technology":[17,80],"to":[18,45,78,111,141],"alleviate":[19],"performance":[20],"and":[21,116,122],"power":[22],"related":[23],"issues":[24,76],"raised":[25],"by":[26,64,157,177],"interconnects":[27],"nanometer":[29],"CMOS.":[30],"Physical":[31],"synthesis":[32,69,85,98,103,134],"for":[33,96],"is":[36,165,175],"substantially":[37],"different":[38],"from":[39],"traditional":[40,132,143],"planar":[41],"due":[44],"presence":[47],"additional":[49],"constraints":[50],"placing":[52],"circuit":[53],"blocks":[54],"multiple":[56,112],"die.":[57],"To":[58],"realize":[59],"full":[61],"potential":[62],"offered":[63],"circuits,":[67],"high-level":[68,97,133],"these":[71,138],"must":[73],"take":[74],"layout-related":[75],"unique":[77],"3-D":[79,91,114,144],"into":[81],"account":[82],"during":[83],"process.":[86],"The":[87],"paper":[88],"presents":[89],"a":[90,142],"layout":[92],"aware":[93],"binding":[94,124],"algorithm":[95,128],"that":[99,136,149],"tightly":[100],"integrates":[101],"tasks":[104],"resource":[106,123],"binding,":[107,146],"assignment":[108],"modules":[110],"die,":[113],"floorplanning,":[115],"inter-die":[117],"via":[118,173],"minimization.":[119],"Since":[120],"floorplanning":[121],"are":[125,181],"interdependent,":[126],"can":[129,152],"significantly":[130],"outperform":[131],"flows":[135],"separate":[137],"tasks.":[139],"Compared":[140],"layout-unaware":[145],"experiments":[147],"show":[148],"approach":[151],"improve":[153],"total":[155],"wire-length":[156],"29%":[158],"on":[159],"average,":[160],"while":[161],"longest":[163],"netlength":[164],"reducedby21%.":[166],"In":[167],"addition,":[168],"number":[170],"through-die":[172],"count":[174],"reduced":[176],"27%.":[178],"These":[179],"optimizations":[180],"achieved":[182],"with":[183],"no":[184],"penalty":[185],"chip":[187],"area":[188]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}