{"id":"https://openalex.org/W2097954739","doi":"https://doi.org/10.1109/isqed.2007.116","title":"Pareto-Front Computation and Automatic Sizing of CPPLLs","display_name":"Pareto-Front Computation and Automatic Sizing of CPPLLs","publication_year":2007,"publication_date":"2007-03-01","ids":{"openalex":"https://openalex.org/W2097954739","doi":"https://doi.org/10.1109/isqed.2007.116","mag":"2097954739"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2007.116","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2007.116","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"8th International Symposium on Quality Electronic Design (ISQED'07)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103009645","display_name":"Jun Zou","orcid":"https://orcid.org/0000-0002-1113-1781"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jun Zou","raw_affiliation_strings":["Institute for Electronic Design Automation, Technical University Munich, Munich, Germany","Inst. for Electron. Design Autom., Techn. Univ. Muenchen, Munich"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Electronic Design Automation, Technical University Munich, Munich, Germany","institution_ids":[]},{"raw_affiliation_string":"Inst. for Electron. Design Autom., Techn. Univ. Muenchen, Munich","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011419637","display_name":"Daniel Mueller-Gritschneder","orcid":"https://orcid.org/0000-0003-0903-631X"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Daniel Mueller","raw_affiliation_strings":["Institute for Electronic Design Automation, Technical University Munich, Munich, Germany","Inst. for Electron. Design Autom., Techn. Univ. Muenchen, Munich"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Electronic Design Automation, Technical University Munich, Munich, Germany","institution_ids":[]},{"raw_affiliation_string":"Inst. for Electron. Design Autom., Techn. Univ. Muenchen, Munich","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033163680","display_name":"Helmut Graeb","orcid":"https://orcid.org/0000-0002-7626-1958"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Helmut Graeb","raw_affiliation_strings":["Institute for Electronic Design Automation, Technical University Munich, Munich, Germany","Inst. for Electron. Design Autom., Techn. Univ. Muenchen, Munich"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Electronic Design Automation, Technical University Munich, Munich, Germany","institution_ids":[]},{"raw_affiliation_string":"Inst. for Electron. Design Autom., Techn. Univ. Muenchen, Munich","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017567485","display_name":"Ulf Schlichtmann","orcid":"https://orcid.org/0000-0003-4431-7619"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ulf Schlichtmann","raw_affiliation_strings":["Institute for Electronic Design Automation, Technical University Munich, Munich, Germany","Inst. for Electron. Design Autom., Techn. Univ. Muenchen, Munich"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Electronic Design Automation, Technical University Munich, Munich, Germany","institution_ids":[]},{"raw_affiliation_string":"Inst. for Electron. Design Autom., Techn. Univ. Muenchen, Munich","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.9929,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.94022704,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"481","last_page":"486"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.7673728466033936},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.7629165649414062},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6637042760848999},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.6130648851394653},{"id":"https://openalex.org/keywords/multi-objective-optimization","display_name":"Multi-objective optimization","score":0.6081598401069641},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5390220880508423},{"id":"https://openalex.org/keywords/pareto-principle","display_name":"Pareto principle","score":0.447752445936203},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4168161153793335},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3832792043685913},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24897581338882446},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1362406313419342}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.7673728466033936},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.7629165649414062},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6637042760848999},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.6130648851394653},{"id":"https://openalex.org/C68781425","wikidata":"https://www.wikidata.org/wiki/Q2052203","display_name":"Multi-objective optimization","level":2,"score":0.6081598401069641},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5390220880508423},{"id":"https://openalex.org/C137635306","wikidata":"https://www.wikidata.org/wiki/Q182667","display_name":"Pareto principle","level":2,"score":0.447752445936203},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4168161153793335},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3832792043685913},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24897581338882446},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1362406313419342},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2007.116","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2007.116","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"8th International Symposium on Quality Electronic Design (ISQED'07)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4300000071525574,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W146784561","https://openalex.org/W634721342","https://openalex.org/W1562942484","https://openalex.org/W1775840686","https://openalex.org/W2078592402","https://openalex.org/W2104147443","https://openalex.org/W2104339053","https://openalex.org/W2106476087","https://openalex.org/W2116235542","https://openalex.org/W2121112734","https://openalex.org/W2126589469","https://openalex.org/W2135281359","https://openalex.org/W2140825526","https://openalex.org/W2141776905","https://openalex.org/W2144133630","https://openalex.org/W2147849504","https://openalex.org/W2153267648","https://openalex.org/W2161332670","https://openalex.org/W2161550080","https://openalex.org/W2162964517","https://openalex.org/W2171568654","https://openalex.org/W2280387905","https://openalex.org/W2470451944","https://openalex.org/W2799067801","https://openalex.org/W4236195134","https://openalex.org/W4249003824","https://openalex.org/W4249323968","https://openalex.org/W6678261945","https://openalex.org/W6719807708","https://openalex.org/W6750391332"],"related_works":["https://openalex.org/W2090178682","https://openalex.org/W2001591765","https://openalex.org/W4241467429","https://openalex.org/W2073147994","https://openalex.org/W1588199609","https://openalex.org/W2384474142","https://openalex.org/W3083133203","https://openalex.org/W1550055091","https://openalex.org/W2744462909","https://openalex.org/W1971520370"],"abstract_inverted_index":{"A":[0,91],"comprehensive":[1],"performance":[2,39,62,75],"space":[3,40],"exploration":[4,41],"on":[5],"system":[6,22,55,77],"level":[7],"offers":[8],"designers":[9],"a":[10,24,30,98,108],"fast":[11],"way":[12],"to":[13,46,51,97],"get":[14],"insight":[15],"into":[16],"the":[17,20,47,52,61,74,121,126],"capability":[18],"of":[19,63,125],"whole":[21,53],"for":[23],"given":[25],"technology.":[26],"The":[27,58,100],"authors":[28],"consider":[29],"charge-pump":[31],"phase-locked":[32],"loop":[33],"(CPPLL)":[34],"system.":[35],"In":[36],"this":[37],"paper":[38],"is":[42,95],"applied":[43,96],"not":[44],"only":[45],"building":[48,64],"blocks":[49],"but":[50],"CPPLL":[54],"as":[56,88],"well.":[57],"trade-offs":[59],"in":[60,71,107,115],"blocks,":[65],"e.g.":[66,79],"gain,":[67],"jitter":[68],"and":[69,73,83,111,123],"power":[70],"VCO,":[72],"at":[76],"level,":[78],"bandwidth,":[80],"locking":[81],"time":[82],"jitter,":[84],"will":[85],"be":[86,113],"represented":[87],"Pareto-optimal":[89],"fronts.":[90],"hierarchical":[92],"optimization":[93],"method":[94,128],"CPPLL.":[99],"sizing":[101],"process":[102],"satisfies":[103],"different":[104],"application":[105],"requirements":[106],"flexible":[109],"manner":[110],"can":[112],"accomplished":[114],"some":[116],"hours.":[117],"Experimental":[118],"results":[119],"show":[120],"efficacy":[122],"efficiency":[124],"presented":[127]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
