{"id":"https://openalex.org/W2154773559","doi":"https://doi.org/10.1109/isqed.2006.137","title":"Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic","display_name":"Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic","publication_year":2006,"publication_date":"2006-04-07","ids":{"openalex":"https://openalex.org/W2154773559","doi":"https://doi.org/10.1109/isqed.2006.137","mag":"2154773559"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2006.137","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2006.137","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"7th International Symposium on Quality Electronic Design (ISQED'06)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006585147","display_name":"Praveen Elakkumanan","orcid":null},"institutions":[{"id":"https://openalex.org/I63190737","display_name":"University at Buffalo, State University of New York","ror":"https://ror.org/01y64my43","country_code":"US","type":"education","lineage":["https://openalex.org/I63190737"]},{"id":"https://openalex.org/I57206974","display_name":"New York University","ror":"https://ror.org/0190ak572","country_code":"US","type":"education","lineage":["https://openalex.org/I57206974"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"P. Elakkumanan","raw_affiliation_strings":["Department of Computer Science & Engineering, State University of New York, University at Buffalo, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science & Engineering, State University of New York, University at Buffalo, USA","institution_ids":["https://openalex.org/I63190737","https://openalex.org/I57206974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083253819","display_name":"Kailash Prasad","orcid":"https://orcid.org/0000-0002-4873-7728"},"institutions":[{"id":"https://openalex.org/I63190737","display_name":"University at Buffalo, State University of New York","ror":"https://ror.org/01y64my43","country_code":"US","type":"education","lineage":["https://openalex.org/I63190737"]},{"id":"https://openalex.org/I57206974","display_name":"New York University","ror":"https://ror.org/0190ak572","country_code":"US","type":"education","lineage":["https://openalex.org/I57206974"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Prasad","raw_affiliation_strings":["Department of Computer Science & Engineering, State University of New York, University at Buffalo, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science & Engineering, State University of New York, University at Buffalo, USA","institution_ids":["https://openalex.org/I63190737","https://openalex.org/I57206974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5080965835","display_name":"R. Sridhar","orcid":"https://orcid.org/0009-0006-8070-5511"},"institutions":[{"id":"https://openalex.org/I57206974","display_name":"New York University","ror":"https://ror.org/0190ak572","country_code":"US","type":"education","lineage":["https://openalex.org/I57206974"]},{"id":"https://openalex.org/I63190737","display_name":"University at Buffalo, State University of New York","ror":"https://ror.org/01y64my43","country_code":"US","type":"education","lineage":["https://openalex.org/I63190737"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Sridhar","raw_affiliation_strings":["Department of Computer Science & Engineering, State University of New York, University at Buffalo, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science & Engineering, State University of New York, University at Buffalo, USA","institution_ids":["https://openalex.org/I63190737","https://openalex.org/I57206974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5006585147"],"corresponding_institution_ids":["https://openalex.org/I57206974","https://openalex.org/I63190737"],"apc_list":null,"apc_paid":null,"fwci":5.6414,"has_fulltext":false,"cited_by_count":27,"citation_normalized_percentile":{"value":0.96057623,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"617","last_page":"624"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9947999715805054,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9922999739646912,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.8389686346054077},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.7479212284088135},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6606018543243408},{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.5985124707221985},{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.5894749760627747},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.575081467628479},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.49575075507164},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.4900747537612915},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4653635323047638},{"id":"https://openalex.org/keywords/cyclic-redundancy-check","display_name":"Cyclic redundancy check","score":0.4525153636932373},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4293779730796814},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.41269010305404663},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.40193307399749756},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.400682270526886},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.36144182085990906},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33841657638549805},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.33532196283340454},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24128401279449463},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.15736526250839233},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.12721359729766846},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.07226517796516418}],"concepts":[{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.8389686346054077},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.7479212284088135},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6606018543243408},{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.5985124707221985},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.5894749760627747},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.575081467628479},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.49575075507164},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.4900747537612915},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4653635323047638},{"id":"https://openalex.org/C137627569","wikidata":"https://www.wikidata.org/wiki/Q245471","display_name":"Cyclic redundancy check","level":3,"score":0.4525153636932373},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4293779730796814},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.41269010305404663},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40193307399749756},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.400682270526886},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.36144182085990906},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33841657638549805},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.33532196283340454},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24128401279449463},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.15736526250839233},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.12721359729766846},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.07226517796516418},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C548081761","wikidata":"https://www.wikidata.org/wiki/Q180388","display_name":"Waste management","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2006.137","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2006.137","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"7th International Symposium on Quality Electronic Design (ISQED'06)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W117147670","https://openalex.org/W1541786636","https://openalex.org/W2011042355","https://openalex.org/W2050431855","https://openalex.org/W2096294684","https://openalex.org/W2096845063","https://openalex.org/W2096927458","https://openalex.org/W2104677471","https://openalex.org/W2127107529","https://openalex.org/W2143253204","https://openalex.org/W2162465831","https://openalex.org/W2165911142","https://openalex.org/W2167002145","https://openalex.org/W2567458453","https://openalex.org/W4236432903","https://openalex.org/W6604745190"],"related_works":["https://openalex.org/W29481652","https://openalex.org/W4248668797","https://openalex.org/W2110968362","https://openalex.org/W4238178324","https://openalex.org/W3141297747","https://openalex.org/W818963952","https://openalex.org/W1939541994","https://openalex.org/W1603944672","https://openalex.org/W1851795671","https://openalex.org/W2146663621"],"abstract_inverted_index":{"With":[0],"technology":[1,38],"scaling,":[2],"combinational":[3,23],"logic":[4,24],"is":[5,67],"becoming":[6],"increasingly":[7],"vulnerable":[8],"to":[9,63],"radiation":[10,65],"strikes.":[11],"Classical":[12],"fault":[13],"tolerant":[14,89],"techniques":[15],"mainly":[16],"address":[17],"single":[18,29],"even":[19],"upsets":[20],"(SEUs).":[21],"Robust":[22],"designs":[25],"capable":[26],"of":[27],"tolerating":[28],"event":[30],"transients":[31],"(SETs)":[32],"also":[33,108],"are":[34,107],"needed":[35],"in":[36,103],"lower":[37],"nodes.":[39],"In":[40],"this":[41],"paper,":[42],"we":[43],"present":[44],"a":[45],"novel":[46],"SET":[47,78,88],"mitigation":[48],"scheme":[49],"for":[50,77],"flip-flops":[51],"based":[52],"on":[53],"the":[54,64,83,86,100],"time":[55],"redundancy":[56],"principle.":[57],"The":[58],"incurred":[59],"area":[60,101],"overhead":[61],"due":[62],"hardening":[66],"minimized":[68],"by":[69,82],"reusing":[70],"existing":[71,74],"components":[72],"(uses":[73],"scan":[75],"portion":[76],"tolerance).":[79],"As":[80],"shown":[81],"simulation":[84,96],"results,":[85],"proposed":[87],"flip-flop":[90],"has":[91],"no":[92],"performance":[93],"overheads":[94,102],"and":[95],"results":[97],"that":[98],"show":[99],"ISCAS":[104],"benchmark":[105],"circuits":[106],"presented":[109]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
