{"id":"https://openalex.org/W1662967771","doi":"https://doi.org/10.1109/isqed.2005.97","title":"Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis","display_name":"Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis","publication_year":2005,"publication_date":"2005-03-31","ids":{"openalex":"https://openalex.org/W1662967771","doi":"https://doi.org/10.1109/isqed.2005.97","mag":"1662967771"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2005.97","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2005.97","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Sixth International Symposium on Quality of Electronic Design (ISQED'05)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085744004","display_name":"Dong\u2010Ku Kang","orcid":"https://orcid.org/0000-0003-1261-6446"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Dongku Kang","raw_affiliation_strings":["ECE, Purdue University, West Lafayette, IN, USA","Purdue University West Lafayette IN USA"],"affiliations":[{"raw_affiliation_string":"ECE, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Purdue University West Lafayette IN USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058073627","display_name":"Yiran Chen","orcid":"https://orcid.org/0000-0002-1486-8412"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yiran Chen","raw_affiliation_strings":["ECE, Purdue University, West Lafayette, IN, USA","Purdue University West Lafayette IN USA"],"affiliations":[{"raw_affiliation_string":"ECE, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Purdue University West Lafayette IN USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031161187","display_name":"Kaushik Roy","orcid":"https://orcid.org/0009-0002-3375-2877"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Roy","raw_affiliation_strings":["ECE, Purdue University, West Lafayette, IN, USA","Purdue University West Lafayette IN USA"],"affiliations":[{"raw_affiliation_string":"ECE, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Purdue University West Lafayette IN USA","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5085744004"],"corresponding_institution_ids":["https://openalex.org/I219193219"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.07232732,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"48","last_page":"53"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6349509954452515},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.5783241987228394},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.48809802532196045},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4702303111553192},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.4678044617176056},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.4506981670856476},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.41964471340179443},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.4191366136074066},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.41602906584739685},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4114057421684265},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.26116639375686646},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.254783034324646},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.22262370586395264},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.10683199763298035},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.09662434458732605},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08828139305114746}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6349509954452515},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.5783241987228394},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.48809802532196045},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4702303111553192},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.4678044617176056},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.4506981670856476},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.41964471340179443},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.4191366136074066},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.41602906584739685},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4114057421684265},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.26116639375686646},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.254783034324646},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.22262370586395264},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.10683199763298035},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.09662434458732605},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08828139305114746},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2005.97","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2005.97","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Sixth International Symposium on Quality of Electronic Design (ISQED'05)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W127069151","https://openalex.org/W1521840072","https://openalex.org/W1616047807","https://openalex.org/W2057108708","https://openalex.org/W2090694109","https://openalex.org/W2105560148","https://openalex.org/W2112148124","https://openalex.org/W2124352222","https://openalex.org/W2144665959","https://openalex.org/W2144699832","https://openalex.org/W2147126729","https://openalex.org/W2154462472","https://openalex.org/W3023540311","https://openalex.org/W4233090922","https://openalex.org/W4253058520"],"related_works":["https://openalex.org/W2055008360","https://openalex.org/W1500063550","https://openalex.org/W2135118255","https://openalex.org/W2133901311","https://openalex.org/W2087871358","https://openalex.org/W2136768364","https://openalex.org/W4386643835","https://openalex.org/W2120361800","https://openalex.org/W2182445672","https://openalex.org/W2146867217"],"abstract_inverted_index":{"As":[0],"technology":[1],"scales":[2],"down,":[3],"power":[4,20,30,52,82],"supply":[5,21,31,53,76,83],"noise":[6,32,54,84],"is":[7,55],"becoming":[8],"a":[9,19,47,66],"performance":[10],"and":[11,43],"reliability":[12],"bottleneck":[13],"in":[14,33],"modern":[15],"VLSI.":[16],"We":[17],"propose":[18],"noise-aware":[22],"design":[23,36],"methodology":[24,80],"for":[25],"high-level":[26],"synthesis.":[27],"By":[28],"evaluating":[29],"the":[34,38,51,59,63,78],"early":[35],"stage,":[37],"proposed":[39,79],"method":[40],"generates":[41],"schedule":[42],"resource":[44],"allocation":[45],"with":[46],"floorplan":[48],"such":[49],"that":[50,72],"minimized.":[56],"To":[57],"achieve":[58],"goal,":[60],"we":[61],"formulated":[62],"problem":[64],"using":[65],"genetic":[67],"algorithm.":[68],"Compared":[69],"to":[70,86],"designs":[71],"do":[73],"not":[74],"consider":[75],"noise,":[77],"reduces":[81],"up":[85],"44%.":[87]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
