{"id":"https://openalex.org/W1702835356","doi":"https://doi.org/10.1109/isqed.2005.65","title":"In-Circuit Self-Tuning of Clock Latencies","display_name":"In-Circuit Self-Tuning of Clock Latencies","publication_year":2005,"publication_date":"2005-03-31","ids":{"openalex":"https://openalex.org/W1702835356","doi":"https://doi.org/10.1109/isqed.2005.65","mag":"1702835356"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2005.65","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2005.65","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Sixth International Symposium on Quality of Electronic Design (ISQED'05)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5046594397","display_name":"Kambiz Rahimi","orcid":null},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"K. Rahimi","raw_affiliation_strings":["Department of Electrical Engineering, University of Washington, Seattle, WA, USA","Dept. of Electr. Eng., Univ. of Washington, Seattle, WA, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Washington, Seattle, WA, USA","institution_ids":["https://openalex.org/I201448701"]},{"raw_affiliation_string":"Dept. of Electr. Eng., Univ. of Washington, Seattle, WA, USA#TAB#","institution_ids":["https://openalex.org/I201448701"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020745504","display_name":"C. Diorio","orcid":null},"institutions":[{"id":"https://openalex.org/I58610484","display_name":"Seattle University","ror":"https://ror.org/02jqc0m91","country_code":"US","type":"education","lineage":["https://openalex.org/I58610484"]},{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C. Diorio","raw_affiliation_strings":["Department of Computer Science and Engineering, University of Washington, Seattle, WA, USA","University of Washington , Seattle"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, University of Washington, Seattle, WA, USA","institution_ids":["https://openalex.org/I201448701"]},{"raw_affiliation_string":"University of Washington , Seattle","institution_ids":["https://openalex.org/I58610484","https://openalex.org/I201448701"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5046594397"],"corresponding_institution_ids":["https://openalex.org/I201448701"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.07499909,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"24","issue":null,"first_page":"396","last_page":"401"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.5982434153556824},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.5705867409706116},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.5256869792938232},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5051384568214417},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.4951252043247223},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.4737083613872528},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.46775174140930176},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4588854908943176},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.450234055519104},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4230315685272217},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.36873528361320496},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.17841562628746033},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11856129765510559}],"concepts":[{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.5982434153556824},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.5705867409706116},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.5256869792938232},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5051384568214417},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.4951252043247223},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.4737083613872528},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.46775174140930176},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4588854908943176},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.450234055519104},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4230315685272217},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.36873528361320496},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.17841562628746033},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11856129765510559}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2005.65","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2005.65","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Sixth International Symposium on Quality of Electronic Design (ISQED'05)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W204812904","https://openalex.org/W1572287951","https://openalex.org/W2011778848","https://openalex.org/W2033443176","https://openalex.org/W2075086017","https://openalex.org/W2097544821","https://openalex.org/W2135347849","https://openalex.org/W2140823559","https://openalex.org/W2152833313","https://openalex.org/W2153489710","https://openalex.org/W2157398460","https://openalex.org/W4236432903"],"related_works":["https://openalex.org/W2174922170","https://openalex.org/W2088914741","https://openalex.org/W3006003651","https://openalex.org/W2133326759","https://openalex.org/W2040807843","https://openalex.org/W4247180033","https://openalex.org/W4249038728","https://openalex.org/W1564063853","https://openalex.org/W2559451387","https://openalex.org/W4230501858"],"abstract_inverted_index":{"Random":[0],"manufacturing":[1,26],"variations":[2,27],"and":[3,15,18,28,40,102,139],"changes":[4],"in":[5],"operating":[6,34,90],"conditions":[7,35],"can":[8,112],"alter":[9],"the":[10,53,99,124],"relative":[11,23],"timing":[12,20],"of":[13,25,33,46,52,75,81,85,123],"data":[14],"clock":[16,47,73,86,115,125,158],"signals":[17],"cause":[19],"violations.":[21],"Increasing":[22],"magnitude":[24],"accommodating":[29],"a":[30,149],"wide":[31],"range":[32],"necessitate":[36],"large":[37],"design":[38],"margins":[39],"decrease":[41],"circuit":[42],"performance.":[43,162],"In-circuit":[44],"tuning":[45,150],"latencies":[48,74,87,116,159],"allows":[49],"recovering":[50],"some":[51],"performance":[54],"loss.":[55],"In":[56],"this":[57],"paper,":[58],"we":[59],"introduce":[60],"self-tuning":[61],"adaptive-delay":[62],"sequential":[63],"elements":[64],"(SASE)":[65],"that":[66,110,131,155],"use":[67,93],"PMOS":[68],"floating":[69],"gates":[70],"to":[71,97,136,160],"tune":[72,113],"individual":[76],"flip-flops.":[77],"SASE":[78,100,111,132,157],"are":[79,134],"capable":[80],"concurrent,":[82],"in-circuit":[83],"optimization":[84],"under":[88],"varying":[89],"conditions.":[91],"We":[92,146],"an":[94],"explicit-pulsed":[95],"flip-flop":[96],"present":[98,148],"operations":[101],"tuning.":[103],"Our":[104,127],"experiments":[105,128],"with":[106,117],"fabricated":[107],"prototypes":[108],"show":[109,130],"their":[114],"picosecond":[118],"resolution":[119],"over":[120],"one":[121],"half":[122],"period.":[126],"also":[129,147],"sensitivities":[133],"comparable":[135],"non-adaptive":[137],"flip-flops":[138],"do":[140],"not":[141],"pose":[142],"any":[143],"practical":[144],"limitations.":[145],"procedure":[151],"for":[152],"pipeline":[153],"circuits":[154],"tunes":[156],"maximize":[161]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}