{"id":"https://openalex.org/W2095257535","doi":"https://doi.org/10.1109/ispa.2012.32","title":"ReKonf: A Reconfigurable Adaptive ManyCore Architecture","display_name":"ReKonf: A Reconfigurable Adaptive ManyCore Architecture","publication_year":2012,"publication_date":"2012-07-01","ids":{"openalex":"https://openalex.org/W2095257535","doi":"https://doi.org/10.1109/ispa.2012.32","mag":"2095257535"},"language":"en","primary_location":{"id":"doi:10.1109/ispa.2012.32","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ispa.2012.32","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 10th International Symposium on Parallel and Distributed Processing with Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108405886","display_name":"Rajesh Kumar Pal","orcid":null},"institutions":[{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Rajesh Kumar Pal","raw_affiliation_strings":["Indian Institute of Technology Delhi, India","Indian Institute of Technology , Delhi , India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Delhi, India","institution_ids":["https://openalex.org/I68891433"]},{"raw_affiliation_string":"Indian Institute of Technology , Delhi , India","institution_ids":["https://openalex.org/I68891433"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085835894","display_name":"Kolin Paul","orcid":"https://orcid.org/0000-0001-6970-5509"},"institutions":[{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Kolin Paul","raw_affiliation_strings":["Indian Institute of Technology Delhi, India","Indian Institute of Technology , Delhi , India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Delhi, India","institution_ids":["https://openalex.org/I68891433"]},{"raw_affiliation_string":"Indian Institute of Technology , Delhi , India","institution_ids":["https://openalex.org/I68891433"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109883707","display_name":"Sanjiva Prasad","orcid":null},"institutions":[{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sanjiva Prasad","raw_affiliation_strings":["Indian Institute of Technology Delhi, India","Indian Institute of Technology , Delhi , India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Delhi, India","institution_ids":["https://openalex.org/I68891433"]},{"raw_affiliation_string":"Indian Institute of Technology , Delhi , India","institution_ids":["https://openalex.org/I68891433"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5108405886"],"corresponding_institution_ids":["https://openalex.org/I68891433"],"apc_list":null,"apc_paid":null,"fwci":1.4503,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.82162263,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"182","last_page":"191"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8233160376548767},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.6878829002380371},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6641209125518799},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6552407741546631},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5432421565055847},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.504459023475647},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4921776354312897},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.45286744832992554},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3639647364616394},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.32805711030960083},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.1857917606830597}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8233160376548767},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6878829002380371},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6641209125518799},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6552407741546631},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5432421565055847},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.504459023475647},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4921776354312897},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.45286744832992554},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3639647364616394},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.32805711030960083},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.1857917606830597},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ispa.2012.32","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ispa.2012.32","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 10th International Symposium on Parallel and Distributed Processing with Applications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":36,"referenced_works":["https://openalex.org/W1499156209","https://openalex.org/W1975116854","https://openalex.org/W1980419087","https://openalex.org/W2008979719","https://openalex.org/W2014809728","https://openalex.org/W2047043979","https://openalex.org/W2082231876","https://openalex.org/W2103518090","https://openalex.org/W2104617021","https://openalex.org/W2109631284","https://openalex.org/W2111386530","https://openalex.org/W2121082877","https://openalex.org/W2124173332","https://openalex.org/W2124350608","https://openalex.org/W2133004230","https://openalex.org/W2135050419","https://openalex.org/W2135089498","https://openalex.org/W2143773524","https://openalex.org/W2145021036","https://openalex.org/W2145252892","https://openalex.org/W2148882055","https://openalex.org/W2162148292","https://openalex.org/W2163916557","https://openalex.org/W2169855483","https://openalex.org/W2170256087","https://openalex.org/W2243416539","https://openalex.org/W2545380179","https://openalex.org/W4231183338","https://openalex.org/W4238549726","https://openalex.org/W4244034697","https://openalex.org/W4248500376","https://openalex.org/W4250486818","https://openalex.org/W6629799285","https://openalex.org/W6662088896","https://openalex.org/W6690457156","https://openalex.org/W6729031703"],"related_works":["https://openalex.org/W2326041751","https://openalex.org/W1977539175","https://openalex.org/W2008368885","https://openalex.org/W2014530133","https://openalex.org/W2337418885","https://openalex.org/W4207012101","https://openalex.org/W2167303720","https://openalex.org/W2497617944","https://openalex.org/W1563139915","https://openalex.org/W2109715593"],"abstract_inverted_index":{"The":[0],"\"one-architecture-fits-all\"":[1],"design":[2],"philosophy":[3],"is":[4],"inadequate":[5],"for":[6,25,99,145],"catering":[7],"to":[8,44,120,131],"the":[9,51,63,95,142],"diverse":[10],"characteristics":[11],"of":[12,22,28,59,85],"applications":[13,87,101],"running":[14],"on":[15,50,88],"manyCore":[16,23,36,159],"architectures.":[17,160],"After":[18],"evaluating":[19],"various":[20,86],"configurations":[21,49],"architectures":[24],"a":[26,33,89,134],"variety":[27],"applications,":[29],"we":[30],"designed":[31],"ReKonf,":[32],"reconfigurable":[34,42,156],"adaptive":[35],"architecture.":[37],"ReKonf":[38,61],"dynamically":[39],"configures":[40],"its":[41],"components":[43,152],"morph":[45],"into":[46,105],"significantly":[47],"different":[48],"same":[52],"architecture":[53,64,97,151],"by":[54,65,140],"continuously":[55],"monitoring":[56],"vital":[57],"parameters":[58],"applications.":[60],"adapts":[62],"tracking":[66],"core":[67],"utilization,":[68],"live":[69],"cache":[70,73],"utilization":[71],"and":[72,115],"sharing":[74],"between":[75],"threads,":[76],"at":[77],"runtime":[78],"without":[79],"losing":[80],"execution":[81],"state.":[82],"Our":[83,124],"evaluation":[84],"cycle":[90],"accurate":[91],"simulator":[92],"shows":[93],"that":[94,127,153],"(reconfigurable)":[96],"suitable":[98],"such":[100],"can":[102,137],"be":[103,138,155],"classified":[104],"three":[106],"main":[107],"variants:":[108],"Chip":[109],"Multiprocessor":[110,113],"mode;":[111,114],"Symmetric":[112],"Clustered":[116],"mode,":[117],"with":[118],"up":[119],"256":[121],"processing":[122],"cores.":[123],"results":[125],"show":[126],"improvements":[128],"from":[129],"32%":[130],"72%":[132],"over":[133],"baseline":[135],"configuration":[136,144],"observed":[139],"choosing":[141],"right":[143],"an":[146],"application.":[147],"We":[148],"also":[149],"propose":[150],"should":[154],"in":[157],"future":[158]},"counts_by_year":[{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
