{"id":"https://openalex.org/W4411724959","doi":"https://doi.org/10.1109/iscas56072.2025.11044182","title":"Dynamic-Window DAC Switching in SAR ADCs and its Mismatch Modelling for High Peak-to-Average Ratio Input Signals","display_name":"Dynamic-Window DAC Switching in SAR ADCs and its Mismatch Modelling for High Peak-to-Average Ratio Input Signals","publication_year":2025,"publication_date":"2025-05-25","ids":{"openalex":"https://openalex.org/W4411724959","doi":"https://doi.org/10.1109/iscas56072.2025.11044182"},"language":"en","primary_location":{"id":"doi:10.1109/iscas56072.2025.11044182","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11044182","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://ris.utwente.nl/ws/files/508405113/Dynamic-Window_DAC_Switching_in_SAR_ADCs_and_its_Mismatch_Modelling_for_High_Peak-to-Average_Ratio_Input_Signals.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5076505253","display_name":"Anojh Kumaran Rajendra","orcid":"https://orcid.org/0009-0000-6339-7808"},"institutions":[{"id":"https://openalex.org/I94624287","display_name":"University of Twente","ror":"https://ror.org/006hf6230","country_code":"NL","type":"education","lineage":["https://openalex.org/I94624287"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"A.K. Rajendra","raw_affiliation_strings":["University of Twente,Integrated Circuit Design Group,The Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Twente,Integrated Circuit Design Group,The Netherlands","institution_ids":["https://openalex.org/I94624287"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5118663992","display_name":"J. Freriksen","orcid":null},"institutions":[{"id":"https://openalex.org/I94624287","display_name":"University of Twente","ror":"https://ror.org/006hf6230","country_code":"NL","type":"education","lineage":["https://openalex.org/I94624287"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"J. Freriksen","raw_affiliation_strings":["University of Twente,Integrated Circuit Design Group,The Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Twente,Integrated Circuit Design Group,The Netherlands","institution_ids":["https://openalex.org/I94624287"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007799241","display_name":"H.S. Bindra","orcid":null},"institutions":[{"id":"https://openalex.org/I94624287","display_name":"University of Twente","ror":"https://ror.org/006hf6230","country_code":"NL","type":"education","lineage":["https://openalex.org/I94624287"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"H.S. Bindra","raw_affiliation_strings":["University of Twente,Integrated Circuit Design Group,The Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Twente,Integrated Circuit Design Group,The Netherlands","institution_ids":["https://openalex.org/I94624287"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I94624287"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12078551,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/window","display_name":"Window (computing)","score":0.6576468348503113},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.560840904712677},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3998397886753082},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15333473682403564}],"concepts":[{"id":"https://openalex.org/C2778751112","wikidata":"https://www.wikidata.org/wiki/Q835016","display_name":"Window (computing)","level":2,"score":0.6576468348503113},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.560840904712677},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3998397886753082},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15333473682403564},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas56072.2025.11044182","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11044182","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:ris.utwente.nl:openaire_cris_publications/82692c44-c91e-46d4-8a0d-29bb09694904","is_oa":true,"landing_page_url":"https://research.utwente.nl/en/publications/82692c44-c91e-46d4-8a0d-29bb09694904","pdf_url":"https://ris.utwente.nl/ws/files/508405113/Dynamic-Window_DAC_Switching_in_SAR_ADCs_and_its_Mismatch_Modelling_for_High_Peak-to-Average_Ratio_Input_Signals.pdf","source":{"id":"https://openalex.org/S4406922991","display_name":"University of Twente Research Information","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Rajendra, A K, Freriksen, J & Bindra, H S 2025, Dynamic-Window DAC Switching in SAR ADCs and its Mismatch Modelling for High Peak-to-Average Ratio Input Signals. in ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings. Proceedings - IEEE International Symposium on Circuits and Systems, IEEE, IEEE International Symposium on Circuits and Systems, ISCAS 2025, London, United Kingdom, 25/05/25. https://doi.org/10.1109/ISCAS56072.2025.11044182","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:ris.utwente.nl:openaire_cris_publications/82692c44-c91e-46d4-8a0d-29bb09694904","is_oa":true,"landing_page_url":"https://research.utwente.nl/en/publications/82692c44-c91e-46d4-8a0d-29bb09694904","pdf_url":"https://ris.utwente.nl/ws/files/508405113/Dynamic-Window_DAC_Switching_in_SAR_ADCs_and_its_Mismatch_Modelling_for_High_Peak-to-Average_Ratio_Input_Signals.pdf","source":{"id":"https://openalex.org/S4406922991","display_name":"University of Twente Research Information","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Rajendra, A K, Freriksen, J & Bindra, H S 2025, Dynamic-Window DAC Switching in SAR ADCs and its Mismatch Modelling for High Peak-to-Average Ratio Input Signals. in ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings. Proceedings - IEEE International Symposium on Circuits and Systems, IEEE, IEEE International Symposium on Circuits and Systems, ISCAS 2025, London, United Kingdom, 25/05/25. https://doi.org/10.1109/ISCAS56072.2025.11044182","raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4411724959.pdf","grobid_xml":"https://content.openalex.org/works/W4411724959.grobid-xml"},"referenced_works_count":9,"referenced_works":["https://openalex.org/W1980893811","https://openalex.org/W2070631620","https://openalex.org/W2101004723","https://openalex.org/W2131792101","https://openalex.org/W2159346009","https://openalex.org/W2532663989","https://openalex.org/W2778109610","https://openalex.org/W4226432265","https://openalex.org/W4312298727"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W2390901981","https://openalex.org/W2390279801","https://openalex.org/W2109115373","https://openalex.org/W4391913857","https://openalex.org/W2358668433","https://openalex.org/W4396701345","https://openalex.org/W2376932109"],"abstract_inverted_index":{"This":[0,79],"paper":[1],"presents":[2],"a":[3,46,87,110,129,141,147],"novel":[4],"Dynamic-Window":[5],"(DW)":[6],"Digital-to-Analog":[7],"Converter":[8,24],"(DAC)":[9],"switching":[10],"technique":[11],"to":[12,61,157,202],"enhance":[13],"the":[14,18,32,37,40,67,73,82,179,184],"power":[15],"efficiency":[16],"of":[17,58,66,126,181],"Successive":[19],"Approximation":[20],"Register":[21],"(SAR)":[22],"Analog-to-Digital":[23],"(ADC).":[25],"DW":[26,52,102,127,168,182,204],"is":[27,53,103],"achieved":[28],"by":[29,36,55,163],"dynamically":[30,71],"adjusting":[31,72],"reference":[33,68],"voltage":[34,69],"used":[35],"DAC":[38,59,159,215],"when":[39],"input":[41,83,144,150],"signal":[42,84,145],"amplitude":[43,85],"falls":[44],"within":[45],"certain":[47],"pre-specified":[48],"window.":[49,78],"The":[50,124,175],"proposed":[51],"implemented":[54,96,207],"choosing":[56],"combinations":[57],"slices":[60],"effectively":[62],"create":[63],"an":[64],"attenuation":[65],"thus":[70],"SAR":[74,132],"ADC\u2019s":[75],"successive":[76],"approximation":[77],"method":[80],"monitors":[81],"using":[86],"coarse":[88],"front-end":[89],"(FE)":[90],"circuit":[91],"that":[92],"can":[93,205],"be":[94,206],"easily":[95],"with":[97,109,146,166,172],"negligibly":[98],"small":[99],"energy":[100,160],"overhead.":[101],"particularly":[104],"energy-efficient":[105],"for":[106,140,214],"real-world":[107],"signals":[108,120],"high":[111,219],"Peak-to-Average":[112],"Ratio":[113,193],"(PAR)":[114],"such":[115,188],"as":[116,189,218,220],"audio":[117],"and":[118,169,191,198],"OFDM":[119],"in":[121,136,183,211],"wireless":[122],"communication.":[123],"effects":[125,180],"on":[128],"12-bit":[130],"1MS/s":[131],"ADC":[133,185,212],"are":[134],"simulated":[135],"MATLAB<sup":[137],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[138],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">\u00ae</sup>":[139],"Gaussian":[142],"distributed":[143],"6\u03c3,":[148],"8\u03c3":[149],"full-scale":[151],"(FS)":[152],"range,":[153],"demonstrating":[154],"its":[155],"ability":[156],"reduce":[158],"consumption":[161],"respectively":[162],"35%,":[164],"41%":[165],"2-level":[167],"45%,":[170],"54%":[171],"4-level":[173],"DW.":[174],"simulations":[176],"also":[177],"explore":[178],"performance":[186,213],"metrics":[187],"Signal-to-Noise":[190],"Distortion":[192],"(SNDR),":[194],"Differential":[195],"Non-Linearity":[196,200],"(DNL),":[197],"Integral":[199],"(INL)":[201],"show":[203],"without":[208],"major":[209],"degradation":[210],"capacitor":[216],"mismatch":[217],"2.5%":[221],"per":[222],"fF.":[223]},"counts_by_year":[],"updated_date":"2026-07-02T09:51:11.867554","created_date":"2025-10-10T00:00:00"}