{"id":"https://openalex.org/W2800011419","doi":"https://doi.org/10.1109/iscas.2018.8350936","title":"Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation","display_name":"Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation","publication_year":2018,"publication_date":"2018-01-01","ids":{"openalex":"https://openalex.org/W2800011419","doi":"https://doi.org/10.1109/iscas.2018.8350936","mag":"2800011419"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2018.8350936","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8350936","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065172476","display_name":"Adeboye Stephen Oyeniran","orcid":"https://orcid.org/0000-0002-6344-3875"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":true,"raw_author_name":"Adeboye Stephen Oyeniran","raw_affiliation_strings":["School of Computer Systems, Tallinn University of Technology, Estonia"],"affiliations":[{"raw_affiliation_string":"School of Computer Systems, Tallinn University of Technology, Estonia","institution_ids":["https://openalex.org/I111112146"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070895334","display_name":"Siavoosh Payandeh Azad","orcid":"https://orcid.org/0000-0001-9177-7779"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":false,"raw_author_name":"Siavoosh Payandeh Azad","raw_affiliation_strings":["School of Computer Systems, Tallinn University of Technology, Estonia"],"affiliations":[{"raw_affiliation_string":"School of Computer Systems, Tallinn University of Technology, Estonia","institution_ids":["https://openalex.org/I111112146"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010536057","display_name":"Raimund Ubar","orcid":"https://orcid.org/0000-0001-8186-4385"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":false,"raw_author_name":"Raimund Ubar","raw_affiliation_strings":["School of Computer Systems, Tallinn University of Technology, Estonia"],"affiliations":[{"raw_affiliation_string":"School of Computer Systems, Tallinn University of Technology, Estonia","institution_ids":["https://openalex.org/I111112146"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5065172476"],"corresponding_institution_ids":["https://openalex.org/I111112146"],"apc_list":null,"apc_paid":null,"fwci":1.7673,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.83842581,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"1","issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6986375451087952},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.6784836053848267},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.6573573350906372},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.6294405460357666},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.6079341173171997},{"id":"https://openalex.org/keywords/segmentation","display_name":"Segmentation","score":0.5741152167320251},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.538347601890564},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.4426713287830353},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4382740259170532},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.43510088324546814},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4186537265777588},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3010023534297943},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2992015779018402},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.22444948554039001},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.18416765332221985},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16930285096168518}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6986375451087952},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.6784836053848267},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.6573573350906372},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.6294405460357666},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.6079341173171997},{"id":"https://openalex.org/C89600930","wikidata":"https://www.wikidata.org/wiki/Q1423946","display_name":"Segmentation","level":2,"score":0.5741152167320251},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.538347601890564},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.4426713287830353},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4382740259170532},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.43510088324546814},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4186537265777588},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3010023534297943},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2992015779018402},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.22444948554039001},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.18416765332221985},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16930285096168518},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2018.8350936","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8350936","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W13277579","https://openalex.org/W1792855452","https://openalex.org/W1956017427","https://openalex.org/W1970313909","https://openalex.org/W2007904745","https://openalex.org/W2026445983","https://openalex.org/W2043949919","https://openalex.org/W2096570353","https://openalex.org/W2097569377","https://openalex.org/W2099117598","https://openalex.org/W2103450206","https://openalex.org/W2108836985","https://openalex.org/W2111907998","https://openalex.org/W2115795793","https://openalex.org/W2120281345","https://openalex.org/W2124267028","https://openalex.org/W2125837930","https://openalex.org/W2127826474","https://openalex.org/W2130323087","https://openalex.org/W2133929141","https://openalex.org/W2140839599","https://openalex.org/W2146797124","https://openalex.org/W2150032667","https://openalex.org/W6600530048","https://openalex.org/W6638215335","https://openalex.org/W6677361912","https://openalex.org/W6678941976","https://openalex.org/W6680725406"],"related_works":["https://openalex.org/W2117563988","https://openalex.org/W2091833418","https://openalex.org/W2120257283","https://openalex.org/W2913077774","https://openalex.org/W2021253405","https://openalex.org/W4256030018","https://openalex.org/W2145089576","https://openalex.org/W1493811107","https://openalex.org/W2154529098","https://openalex.org/W2109319621"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,14],"new":[4],"method":[5,24,52,81],"for":[6],"pseudo-exhaustive":[7],"testing":[8],"of":[9,17,20,73,79],"standard":[10],"array":[11],"multipliers":[12],"using":[13],"novel":[15],"approach":[16,40],"data-controlled":[18],"segmentation":[19],"the":[21,36,74,80],"circuit.":[22],"The":[23,51,70],"covers":[25],"both":[26,83],"combinational":[27],"and":[28,47,62,88],"sequential":[29],"fault":[30,49,67],"classes.":[31],"Differently":[32],"from":[33],"previous":[34],"papers,":[35],"proposed":[37],"separate":[38],"cell-testing":[39],"targets":[41],"multiple":[42],"faults":[43],"in":[44],"different":[45],"cells":[46],"avoids":[48],"masking.":[50],"is":[53],"also":[54],"applicable":[55],"to":[56],"other":[57],"multiplier":[58],"architectures":[59],"like":[60],"Booth":[61],"MiniMIPS":[63],"with":[64],"high":[65],"stuck-at":[66],"(SAF)":[68],"coverage.":[69],"regular":[71],"structure":[72],"test":[75],"allows":[76],"efficient":[77],"implementation":[78],"as":[82],"software":[84],"based":[85],"self-test":[86],"(SBST)":[87],"hardware-based":[89],"BIST.":[90]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}